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Type: Posts; User: carmeloA

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  1. Replies
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    Closed: Re: Advance Training - ZYNQ SOC

    You can find tons of information about the zynq and in particular on eth and usb.
    for example, this is the first googling for Ethernet:...
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    Closed: ARM - Strange PC adress on reset

    Hello Everyone,

    I am just starting with a new board, a landboard with a nxp LPC1768 programmed with an external ulink2 with keil4.

    I do not understand why when i go in debug mode the starting...
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    Closed: Re: Design Constraints in Design Compiler

    The first tips:in order to same power you can use the clock gaiting tecquique by enabling it when you elaborate your design.
    In general, power isn't optimized at syntesis level but at design level...
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    Closed: ARM assembler - loop through registers

    Hi to all,
    how can I loop through each rgister from r0 to r7?
    I have some data in the registers r0:r7 and i want to compare them with a constant; i need to put 8 line of sub and cmp or is there any...
  5. Closed: Re: Help needed to enable Auto Route in Orcad Layout 16.0

    You need an OrCAD PCB Designer Professional license in order to get the autoroute enable as BigBoss sad.
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    Closed: Re: modelsim simulation after syntesis

    Thank you for your reply.
    In my library folder i have 1 file .lib and 1 .db.
    I tried to import them in modelsim but it doesn't recognize as library. Where can i find that verilog file to link in...
  7. Closed: Re: Help needed to enable Auto Route in Orcad Layout 16.0

    You can find the auto route function in the menu:

    Route -> PCB router -> Route Automatic
  8. [SOLVED]Closed: Re: FSM output function of the encoded states

    I manage to solve my problem with the method you have proposed! :-D
    actually it was so simple but i hadn't even thought this solution, maybe because i was so involved in the vhdl that i was focused...
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    Closed: modelsim simulation after syntesis

    Hi to all,
    I wonder if it is possible to simulate a synthesised netlist by design compiler in modelsim.

    I'm finding that after the synthesis of design vision the output is a file with some...
  10. [SOLVED]Closed: FSM output function of the encoded states

    Hi to all,
    I want to build a simple FSM in vhdl where the output is the same of the state encoding of the FSM.
    I want this behaviour because I want to change the state encoding at every syntesis...
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    Closed: [modelsim] tcl script simulation HOWTO

    Hi to everybody,
    I’m a little bit confused about how to simulate an entity on modelsim in tcl.
    I tried to find some guide by googling but i found lots of command that are hard to be understood.
    My...
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    Closed: Re: enable vs reset in digital IC

    Thank you for your replies.
    It's straightforward for a counter, and i can not refear to any datasheet because i'm implementing a fsm in vhdl so i'd like to know the differences between the two...
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    Closed: Re: MPLab not detecting my PIC16F887

    have you connected the pickit 2 properly?
    have a look at this photo:
    http://www.eobdtool.com/editor/attached/20170419/20170419170254_94725.png
    If yes, verify the connection between the programmer...
  14. Replies
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    2,976

    Closed: enable vs reset in digital IC

    Hello everybody,
    I'm a little bit confused about the difference of reset and enable in digital IC...
    for a design point of view, the enable signal helps to prevent glitches at the output port, so...
  15. Closed: Re: Modelsim - Different istance of the same unit

    thanks for your reply. It is not a hierarchical design becouse the registers haven't got any correlation between each other.
    What i'm trying to do is to simulate different block in simulink using...
  16. Closed: Re: Modelsim - Different istance of the same unit

    so your suggestion is to rename the external file by mean of doing multiple copies of the same design unit and import them to modelsim. is this your idea or i'm misunderstanding?

    i wanted to do it...
  17. Closed: Modelsim - Different istance of the same unit

    hello to all,
    anyone know how to import in modelsim different istance of the same design unit?
    such as, if i want to import in my simulation the same register(named register_N), multiple time, so...
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    Closed: Re: modelsim on HPC for faster simulations

    Thanks for your reply.
    So yuou mean that a workstation behave better than a cluster that it is optimized for parallel computing?
    it's possible to do the simulation in a parallel way with modelsim...
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    Closed: modelsim on HPC for faster simulations

    Does anyone know if it is possible to run simulations with modelsim using a high performace computer?
    sometimes i noticiese that for a bunch of milli-seconds the simulation takes minutes. so i am...
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