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    Closed: Re: Field Programmable Transistor Array (FPTA)

    Why not send an e-mail to one or more of the people doing research? That sort of thing actually has been known to work. ;) They might point you in the right direction.
  2. Closed: Re: upcounter and updown counter power and area

    I'd expect that a 6-bit updown counter will take at least as much power/area as 6-bit upcounter, and possibly a bit more. I'd expect area increase to be slightly more pronounced than power increase....
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    Closed: Re: Serial lvds adc ads5263

    You could probe the LCLK or ADCCLK signal to see if you actually get a stable clock there. Seeing your clock signal on an oscilloscope tends to generate "ah hah" moments every now and then. Or if...
  4. Closed: Re: Best ADC to interface with DE2-115 board with parallal data out

    This should get you started:

    http://www.ti.com/lsds/ti/data-converters/analog-to-digital-converter-products.page#p84=8;10&p1089=1000;5000000000

    Not that you should use TI per se, but the...
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    Closed: Re: how to assign values to wire in verilog

    You should show the code for your mac unit.

    Not sure if you should actually be using an assign, but since you ask for it and show no code to base better advice on ......
  6. Closed: Re: How Convert this system verilog code to verilog?

    Looks like assert is the only statement you need to take care of. Several options:

    The "who cares" option. Any decent simulator will handle SV these days. So if your simulator supports SV you...
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    Closed: Re: Adc-fpga-dac interfacing vhdl

    Genius! You incredible ... human, you! Thanks for a good chuckle.

    Allow me to paraphrase: "Yes K-J, you are absolutely right. Getting the testbench in order should really be my priority at this...
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    Closed: Re: how to interface adc with fpga

    And it will also give you an extra perspective on how to write technical documentation. ;-)
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    Closed: Re: systemC language Future

    Nope, no C++ required. You only need it when you want to do stuff that is easier to get done in C++ than in SystemVerilog. And I should add that the I only ever used the C++ part for modeling and...
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    Closed: Re: how to interface adc with fpga

    Suggesting opencores ... now that's just cruel.

    Then again the OP deserves it, so karmically it all evens out.
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    Closed: Re: systemC language Future

    *grin* Not only amusing, but too true as well.

    In addition to Dave's explanation a 100% personal and thus possibly quite random observation...

    Some time ago I tried SystemC along the lines of...
  12. Closed: Re: How to Connect External Memory to Altera FPGA

    Nah. He just doctered the paths and then took a screenshot. That's what I'd do to mess with people. XD


    Good call. I did notice the ZZZ signal in the testbench, but that was hardly unique given...
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    Closed: Re: Bitwidth Management in Input and Output

    Now you spoiled the exercise for the reader. ;)

    But yes, this is a perfect example of why you want to use clock enables.
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    Closed: Re: Bitwidth Management in Input and Output

    Are you sure it's not expectation value error? As in, I could see how you can confuse yourself easily with the simulateously incrementing counters. The reason I ask is that I don't really see...
  15. Closed: Re: SystemVerilog testbench requires a model, how does one verify the model itself?

    I can sortof see the point. You have the main testbench, which is so complex that it needs to be checked and may even need debugging. So to check/debug it you need another testbench to check the main...
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    Closed: Re: i2c transaction question

    Allow me to adjust that transaction list:

    0.1 Start project thinking you want to use I2C.
    0.2 Make list of all the requirements for a high speed multi-master implementation.
    0.3 Start...
  17. Closed: Re: How to Connect External Memory to Altera FPGA

    Confounded! Unfortunately that indeed looks like you described. :(

    In which case I can only echo what ads-ee already said, with bold for added emphasis.
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    Closed: Re: Bitwidth Management in Input and Output

    Edited from an older reply to a post on the same subject...

    What kind of "for loop" do you want? Basically two options:

    1 - Do you want something that loops in time?
    2 - Do you want to unroll...
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    Closed: Re: sending data from PC to FPGA using UART

    Yup, that's pretty much also how I read that post. Either you'll have to add an uart module yourself, or that bluespec software has some pointey clickey capability to add an uart for you.

    For the...
  20. Closed: Re: What are different abstraction level at which stimulus is applied to DUT in testb

    There are higher levels of abstraction than transaction level as you describe it. It is transaction level modeling as other people describe it. ;) TLM is more than just dumping an N-bit word on the...
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    Closed: Re: What is a1() in this verilog-AMS code?

    Look under "Instantiating a module" here: http://www.asic-world.com/verilog/syntax2.html
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    Closed: Re: Where do I find the LEON2 source code?

    Check this repo: https://github.com/Galland/LEON2

    git clone https://github.com/Galland/LEON2.git
  23. Closed: Re: Can any one provide me RTOS code for dspic30f and LCP2148

    Tsk. I could. But I won't. And I hope no-one else does either. Not out of malice. But out of a fervent hope for you to get a chance to improve yourself today. :)

    Just download the source .zip...
  24. Closed: Re: Help Need: Please help me to understand this code

    And regarding code readability, personally I'd write that like so:

    finalGater = scanEn ? testModeEn : (~scanEn ? funcMode : 1'hx);

    That way it's easier to see how the ~scanEn ? funcMode : 1'hx...
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    [SOLVED]Closed: Re: Packet Loss in UDP implemented in FPGA

    *grin* That sounds awfully familiar. Luckily all of these have to do with a large subset of Homo Sapiens being a bunch of stupid mthrfkrs. If you manage to avoid being part of that subset and...
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