Search:

Type: Posts; User: wesleytaylor

Page 1 of 12 1 2 3 4

Search: Search took 0.02 seconds.

  1. Closed: Re: Xilinx synthesis directives within a VHDL 2008 package definition

    Well in my design. IT works for synthesis. However I didn't use xsim for simulation because it couldn't handle vhdl2008.

    Examples of
    if rst then

    killed the xsim. It just cannot handle...
  2. Closed: Re: Xilinx synthesis directives within a VHDL 2008 package definition

    Dpaul, try the following

    constant sim_byte_endian : boolean := false
    -- pragma synthesis_off
    or true...
  3. [SOLVED]Closed: Re: Need help creating Vivado Timing Constraint

    What I've discovered -

    Easiest solution to overcome my problem on a Xilinx device is to instantiate a xpm block - xpm_cdc_single/xpm_cdc_array_single.

    However when trying to be...
  4. [SOLVED]Closed: Need help creating Vivado Timing Constraint

    Hello all,

    Situation is a follows.
    Design in Vivado 2018.4
    Have multiple signals going from clock domain A to clock domain B. I have created a synchronising FF to handle these signals....
  5. [SOLVED]Closed: Re: VHDL scope vs visibility vs visibility by selection

    Thanks Tricky,

    I was aware that the ^ - equivalent to "cd .." - looks up a level.

    However I'm surprised to see that the order of block declarations matter. Although the statements declared...
  6. [SOLVED]Closed: VHDL scope vs visibility vs visibility by selection

    Hello all,

    This following is a derived from my desire to keep a signal declaration local to a specific block, but use it in a different block. I know if I was to move the "scope" of the signal...
  7. Replies
    7
    Views
    583

    Closed: Re: Inferred VHDL dual port RAM template

    process(clk) is
    begin
    if rising_edge(clk) then
    prev_read_addr <= read_addr;
    end if;
    end process;

    process(clk) is
    begin
    if rising_edge(clk) then
  8. Replies
    7
    Views
    583

    Closed: Re: Inferred VHDL dual port RAM template

    How important is portability vs vendor ip instantiation?

    Just a brain dump - Based on the code presented you'll always have to wait 1 cycle after we='1' before your see write value pushed out onto...
  9. Replies
    3
    Views
    299

    Closed: Re: HELP ME the newbie with Verilog Code

    I want to help, but this is blatant offloading of work. How are you going to get any better?

    You need to know the following
    1. You use the clock to generate a counter.
    2. Based on clock speed a...
  10. Closed: Re: Shifting control from one module to another iteratively

    Step 1, create a vector-array of your data
    Step 2, Use generate statements to iteratively connect the previous.


    type x is array<> of std_logic_vector(<>)
    signal data_in : x ... -- note this is...
  11. Closed: Re: Real time voice encryption/decryption with FPGA

    Step1 Make sure you're not using any form of AES like CipherBlockChaining (at least not until you know where you are in the chain)
    Step2 Framing the data as outlined by #3 is a good place to start....
  12. Replies
    10
    Views
    658

    [SOLVED]Closed: Re: Modelsim clock signal

    Sweet. I found it useful for generating a ramp (counter), however interestingly it has no affect on the signal value.
    See picture
    154984

    wave create -pattern counter -startvalue 00000000...
  13. Replies
    10
    Views
    658

    [SOLVED]Closed: Re: Modelsim clock signal

    My version of modelsim/questasim doesn't even have create_wave.

    I have an option called force. In order to create a clock you force a toggle behaviour.

    I don't know where create_wave came from...
  14. Replies
    6
    Views
    766

    Closed: Re: How to compare variables name

    #2 I've noticed vpi handle in the vhdl standard? What is this?

    Is this the way the software processes the rtl code.

    Can you talk to modelsim/questasim or whatever software using these functions?
  15. Replies
    17
    Views
    1,367

    Closed: Re: Advanced VHDL book recommendation

    It's like groundhog day
    https://www.edaboard.com/showthread.php?375881-Is-the-quot-Gaisler-method-quot-of-writing-quot-structured-VHDL-quot-popular&p=1610157

    - - - Updated - - -

    What I would...
  16. Replies
    17
    Views
    1,367

    Closed: Re: Advanced VHDL book recommendation

    If you want to learn VHDL then read something written by Peter Ashenden or a book named as such online.

    If you want to write good structured code then read the following...
  17. Closed: Re: VHDL use of 'Z' std logic for bus, or should one use interconnect?

    Not ...bricked bricked, but dead to comms now. It works when I put the old build on, which used an interconnect setup with a huge slv of dtackbs AND reduced.

    I'm looking at the schematic and it's...
  18. Closed: VHDL use of 'Z' std logic for bus, or should one use interconnect?

    Hello all,

    Basically in simulation land the following works. However the question is can an FPGA handle tristating internally, because on hardware I've just bricked the device.

    OVERSEER takes...
  19. Closed: Re: vcom-1263 Error with generate and component instantiation

    Like many things in life, I'm force to do it through circumstance.

    The legacy code that I've inherited is like the stackoverflow question.

    They used for all statements in the wrong level of...
  20. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    I would like to confirm #8 worked for me.



    module x #(
    parameter sim_path = "string",
    ...
    )(
    ...
    )
  21. Closed: vcom-1263 Error with generate and component instantiation

    First see https://stackoverflow.com/questions/41860693/vhdl-warning-vcom-1263-configuration-specification-all-bcd-applies-to-no

    Now instead of including the

    for all : x use entity lib.x within...
  22. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    Looking at std 1364-2001 section 17. IS the function you're talking about sformat? I tried
    $display("%s", $sformat(my_str, "%s"));

    Needless to say this was a total failure. sim tool was expecting...
  23. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    #6 This is what I got with `define in quotes as per your comment

    Sim path = /home/P_1559_10030/iss_working/workspace/taylow00/simulation/sim_stimulus
    Result path =...
  24. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    #2 As per the `else example, it works, however it's not flexible for other users.

    Situation is : User checkout repo from git. Within their workspace is a test_vectors directory. They develop tests...
  25. [SOLVED]Closed: Creating verilog define for filename based on input file path, string concatenation

    I want to be able to run a simulation with a test vector located in a repository. The repository will be determined by users credentials. The repository will not necessarily be a relative path to...
Results 1 to 25 of 284
Page 1 of 12 1 2 3 4