Type: Posts; User: erikl

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  1. Closed: Re: CMFB biasing current in fully differential Opamp with adaptive current source

    I'd think so, if you want your diff amp react to large signal/step input fast enough.
  2. Closed: Re: Source follower design issue for cascoded two stage op-amp

    Why? The center voltage vo1 should be around VDD/2 (to achieve high swing), so you need that high shift 'cause VSG6 shouldn't get too much overdrive voltage. You can adjust Id6 by its W/L(6) ratio -...
  3. Replies

    Closed: Re: Relating Transmitter dBm to uV/m and EIRP

    14dBm ≙ 25mW, which generates 1.12V @ 50Ω - nearly your stated value.
  4. Closed: Re: Rail to rail input folded operational amplifier

    Depends. I used it for supply voltages of 1.0±0.2V and it worked well, as the Vth voltages of the process suited fine. With higher VDD this simple (but admittedly very elegant, because of its perfect...
  5. Closed: Re: Source follower design issue for cascoded two stage op-amp

    Ok, I see what you mean.

    Did I say that? I wrote weird terminology!
  6. Closed: Re: Why BJT is used for voltage reference and not CMOS

    Actually such a current source produces a PTAT voltage reference, which - by comparison with a second PTAT voltage reference - can be converted into a CTAT current reference.

    A MOSFET can be used...
  7. Closed: Re: Rail to rail input folded operational amplifier

    By W/L ratio (=1) between (P3,P4):(P1,P2) and (N3,N4):(N1,N2) resp. Don't forget: V2 & V3 must be supplied externally. Also, the common drain voltage of P5,N5 (≈VDD/2) supplies all the gates of N3,N4...
  8. Closed: Re: Source follower design issue for cascoded two stage op-amp

    No. The shift of the source follower MT1 of course is VSG (VSG1T in this weird terminology).
  9. Closed: Re: Calibre LVS Extraction Report Warnings Question.

    No, I wouldn't think so.

    The warnings just inform that the power PATHCHK couldn't be performed because of unattached power labels and ports. So the electrical - not the physical! - connectivity...
  10. Closed: Re: In snapback mechanism how voltage reduces when parasitic NPN is turned ON?

    Once the n-p-n turns on means it is conducting and so presents a low resistance to the ESD event. Such an ESD event owns a certain energy E = ∫V(t)*I(t)dt , which is dissipated in that n-p-n...
  11. Closed: Re: Optimized MinCap, Minres values for 10 MHz amp simulation using Spectre

    Due to very probable serial connection of RC elements I'd calculate with the 10-fold frequency, hence 100MHz. So I'd try e.g. with mincap=100fF and minres=16Ω (f = 1/2πRC).
  12. [SOLVED]Closed: Re: Common mode gain simulation for differential amplifier using balun

    In order to stay consistent with Ken Kundert's Test Bench description, you should name the input balun Bi (i for input) and the output balun Bo (o for output).

    Yes, I think so!
  13. [SOLVED]Closed: Re: Common mode gain simulation for differential amplifier using balun

    I think the second paragraph of 3.1 Gain in the a.m. PDF should read (only for the Balun nomenclature of your a.m. picture!):

    To measure the common-mode gain, set the AC magnitude on Vic to 1 V...
  14. Replies

    Closed: Re: ConnectLib files in ams simulation Cadence

    Yes. You have to create your own level converter - if the AMS lib doesn't offer one.
  15. Closed: Re: What is Double Snapback Characteristics in High-Voltage nMOSFETs

    Snapback - in this context - means the sudden receding of the voltage at a certain current, which generates a kink (or a knee) in the I-V characteristic of the device.
  16. Closed: Re: What is the difference between LVS and ERC ?

    - LVS means Layout versus Schematic comparison
    - ERC means Electrical Rules' Check
    - DRC means layout Design Rules' Check

    These all are necessary checks with their own rules' sets. Depending on...
  17. Closed: Re: How to change the m factor (multiplication factor) for Instances in cadence

    Depends on how you want the multiplication be done:

    Either m equal instances of the same device, then instantiate this device <1:m> times in parallel. Or you can multiply it by its Number of...
  18. Replies

    Closed: Re: Current reference design for CS-DAC

    1) I think your wp/wn ratio is too large. Increase your nmos widths, keeping the original w/l ratios.

    2) If you decrease the above widths ratio by this method, you should be able to keep your pmos...
  19. Replies

    Closed: Re: Generate pulses of different widths

    Use a piecewise linear (PWL) voltage-controlled voltage source (VCVS).
    Search for these abbreviations in your C@dence Virtuoso simulation engine docu.
  20. Replies

    Closed: Re: Factors deciding Silicon Wafer Thickness

    1. The wafer diameter (crash (concussion) safety during handling (manual or automatic) )

    2. The dice' separation method (scribe & break, sawing, etching)

    3. As thin as possible (silicon usage)
  21. Replies

    Closed: Re: Calibre Tool for DRC errors

    This depends on:

    - which physical design tool you are using
    - which DRC tool your PDK prefers
    - which (potential) foundry provides their Design Rules' Set for the PDK of your physical design tool
  22. Replies

    Closed: Re: Nand gate using bsim-cmg

    Either hspice didn't find the .include "modelcard.xmos" modelcards, or
    these modelcards do not contain the therein used nmos1 respectively pmos1 models.
  23. Closed: Re: Differences between Wideband & broadband RF Power Amplifiers

    I think so. At least both of them are sometimes used in the same connection. Some companies seem to make a difference regarding the application:

    Pasternack uses broadband amplifiers as...
  24. Replies

    Closed: Re: Nand2 gate in magic vlsi

    Seems you didn't apply a stimulus signal?
  25. Closed: Re: IC layout I/O design------power on control (POC) cell

    Depends. Maybe there's a pad cell available, which creates this signal (e.g. an LDO pad cell which creates the core Vdd from the pad Vddpst voltage. Its "power good" signal could be your POC). If...
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