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  1. Closed: Re: LoopGain analysis with multiple feedback loop

    @FvM,
    Can you elaborate more on this please? I don't understand what you mean here.

    If I don't have the circuit at the bottom, my VLG Middlebrooks analysis will not show a zero but with the...
  2. Closed: Re: LoopGain analysis with multiple feedback loop

    @FvM,

    Thank you for the reply. Indeed I am doing exactly what you specified with my simulations, using VLG and middlebrooks method on both loop, measuring ratio on both sides of VLG. The thing is,...
  3. Closed: Re: LoopGain analysis with multiple feedback loop

    The op-amp is a simple 5 transistor op-amp, with gain of around 40-50dB, the total resistor is around 500K Ohm.
    My schematic looks almost exactly like the sketch I provided except with values of the...
  4. Closed: LoopGain analysis with multiple feedback loop

    Hey guys,

    Please see the sketch of my circuit here.

    157367

    I want to do loop-gain analysis (a.k.a. loop stability analysis) for the top loop. In simulation I simply put a voltage source...
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    Closed: Re: MOSFETs connected in series

    Thank you for the reply @Dominik, much appreciated.

    - - - Updated - - -

    Thanks @sutapanaki for the explanation
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    Closed: Realistic Monte Carlo setup

    Hi All,

    I'm wondering about which Monte Carlo setup will accurately represents statistical distribution in silicon on mass production.

    There are 2 cases that I'm considering:
    Case-1: Global...
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    Closed: Re: MOSFETs connected in series

    @wwfeldman, Thanks for the reply, sorry I don't have reference explanation for you, I'm looking for information myself.

    - - - Updated - - -



    Thanks for the reply.
    Indeed I am referring to...
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    Closed: Re: MOSFETs connected in series

    Here is the sketch: link

    I only drew 3 devices but conceptually they are the same. Basically NMOS connected in series.

    The top most transistor will be in saturation and the other 4 will be in...
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    Closed: MOSFETs connected in series

    Let's say I have 5 NMOS with size W/L connected in series (stacked) with gate connected together, from what I understand this is functionally equivalent to a single NMOS with size W/5L.
    In terms of...
  10. Closed: Re: What is the drawback of operating in subthreshold

    Thank you for the explanation!
    I don't actually intentionally go to subthreshold but the current requirement kinda force me into this region.
    For a standard supply voltage variation (+/- 10%) and...
  11. Closed: What is the drawback of operating in subthreshold

    Specifically, I'm building a constant-gm bias circuit (ie. delta-Vgs) with relatively low current consumption. What are the drawbacks of operating in subthreshold vs saturation?

    I know it will...
  12. Closed: Re: Reducing leakage by applying negative Vgs (NMOS)

    Thanks for the answer.

    Reliance on simulation models were exactly my next thoughts/questions on the subject. I am currently designing a circuit that has negative Vgs and it's critical that the...
  13. Closed: Reducing leakage by applying negative Vgs (NMOS)

    Is it possible to reduce leakage current by applying Vgs=negative (NMOS transistor) instead of Vgs=0? I notice in my simulation that at negative Vgs the leakage current is lower and it is...
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    Thanks for the input.
    Could you elaborate more on this part:


    I don't quite understand what you mean here.
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    OK got it.

    Thanks for the explanation, now I have a better understanding on AVG/RMS.
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    Sorry for not providing a sketch yet, mainly I was unsure on what sketch you required. i did try to draw the vout vs load current to illustrate.

    In any case, I think I am now clear that AVG is the...
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    Hi,

    Is it accurate to treat the digital switching signal similarly to noise? Because the switching occurs periodically on a certain switching frequency unlike noise. It does looks like noise...
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    I actually have all 10 blocks simulated with the LDO so I don't need to extrapolate from 1 to 10, my confusion is rather on whether I should take RMS or AVG of this waveform.

    The waveform looks...
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    Thanks for the answer.
    So it looks like from this equation it is IAVG instead of IRMS, am I interpreting it correctly?

    Just to clarify my initial question, please take a look at this image.
    The...
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    Hmm.... I'm actually not sure what you mean here. The 200MHz current switching seems to load the LDO greatly since I see the output drops immediately when it starts switching.
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    But the current waveform that I'm measuring is from the power supply of digital blocks and are noise-like, for this waveform the RMS and average current value between the same time-range is...
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    Thanks for the answer. I was inclined for RMS because it's the bigger number between the 2, but it's actually much bigger, 3x, so if I am designing based on this my circuit is that much bigger which...
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    Sorry for the late reply, just hit morning here.

    This illustrate what I want to do: Vout vs Iload

    In the X-axis is a sweep of load DC current of the LDO, on the Y-axis is the LDO output. In...
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    Thanks for the reply.
    How about if I want to calculate the current consumption of a switching digital blocks, do I use RMS or AVG?

    Basically I want to make sure that I design the size of my pass...
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    [SOLVED]Closed: Re: Average vs RMS load-current for LDO design

    It's actually 10x of the same digital circuit, so in total they are not so small I guess. The range of RMS current I'm getting is 2.5mA typical and 5mA worst case.
    The circuit itself is a driver...
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