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  1. [SOLVED]Closed: Re: Suppressing the spacing in $fwrite command of Verilog

    That worked. Just mentioning here for the future reference of others.
    @FvM The reference that you gave is the reference that explains what is printing with minimum size. Thanks.
  2. [SOLVED]Closed: Suppressing the spacing in $fwrite command of Verilog

    Hi,

    Please see the code below:


    $fwrite(WglFile, "\tFREFH := input[%dnS:S];", wgl_t_timeplate_FREFH, "\n");


    here wgl_t_timeplate_FREFH is of integer type.
  3. Replies
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    Closed: Inducing delays in WGL files

    Hi,
    I have a Systemverilog Script that is generating WGL script for every testcase that I run for simulation using TCL (do files). The issue is, in Modelsim everything is ideal(no delays)). And I...
  4. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    Spot on.
    But the model I am using is from a world renowned company (and yes shit happens :) ).

    The problem is somewhat solved. Followed your and @dpauls instructions. Put timescale in all files....
  5. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    Meanwhile mods see this thread, let me explain.

    Its kind of a problem with software.

    I wrote some files in Modelsim(in a project).
    Then this project was taken to another computer. That guy...
  6. Closed: Re: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    Mods please delete this thread, posted the same on Intels website.
  7. Closed: Module 'xyz' does not have a timeunit/timeprecision specification in ...

    So the original error in Modelsim is :

    Module 'xyz' does not have a timeunit/timeprecision specification in effect, but other modules do.

    The issue is: I have checked all the files in project,...
  8. [SOLVED]Closed: Re: ModelSim is not reporting errors properly

    You are right. When codes simulated, it gave an error. Thanks.
  9. [SOLVED]Closed: Re: ModelSim is not reporting errors properly

    No, nothing appeared. Basically it is compiling without any error. I don't know why its not detecting errors. It is detecting some other errors, though.
  10. [SOLVED]Closed: ModelSim is not reporting errors properly

    Hi,
    I am using ModelSim 18.1 for the simulation of my designs. Now the problem is I have some fairly obvious mistakes, and upon compile, ModelSim is skipping them and is not reporting the errors.
    ...
  11. Replies
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    [SOLVED]Closed: Re: Hz vs number of bits

    My method is indeed difficult, but explains everything.
  12. Replies
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    [SOLVED]Closed: Hz vs number of bits

    My question is very elementary, yet tricky.

    Say for example: I have a digital clock of 10MHz. I need to trigger an operation at 10ms.

    So how many bits I will be needing, after counting which I...
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    Closed: Re: Writing ModelSim do files

    Actually I am using 2019 ModelSim. I saw that document. But its very very basic. Is there any other resource that I may refer for learning that?
    Another question is : What script that we type on...
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    Closed: Writing ModelSim do files

    I am working on an ASIC design project in ModelSim environment. After designing, it's now verification phase.

    For that I need to write do files.

    There are two problems.

    1) I don't know...
  15. Closed: Single SPI SS to control multiple devices

    I am given a task to design a SPI master module in Verilog (The ultimate goal is to design an sensor ASIC).

    The problem is: I have only four I/Os i.e. MISO, MOSI, SCLK, and SS(single line).
    But...
  16. Closed: Re: [MOVED] Why FPGAs are shipped with optional microcontrollers soft cores

    Complete stack is indeed difficult, and some time impossible due to space constraint, but from Phy till MAC, its pretty normal.
  17. Closed: [MOVED] Why FPGAs are shipped with optional microcontrollers soft cores

    I am an experienced FPGA programmer. I am doing designs using Verilog and VHDL for quite some time, now.
    Till today, one question bugs me a lot, and often. Why every FPGA vendor gives an option of...
  18. Closed: Keil uVision 5 is crashing on startup

    Hi,
    I know this problem has been discussed several times before. But my problem is little different.
    I am using latest version of Keil MDK(just downloaded) on Windows 7 professional, at a laptop...
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    Closed: Re: STM3240G-EVAL bsp files

    You are lucky then!
    Btw, I am following a course, that says DFP and BSP are necessary for MCU+IDE to work properly. So, I was just curious. I have not yet started "work" on that.

    - - - Updated -...
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    Closed: STM3240G-EVAL bsp files

    Hi,
    Actually I am new to the MCU world. I have STM3240G-EVAL board(got from my company), and I am in the process of setting up this board for further use. I am using Keil V5.26.2.0 software for the...
  21. [SOLVED]Closed: Re: Conversion of std_logic to integer in VHDL

    Here is a better version of the same code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use ieee.numeric_std.all;

    entity micro_test_file is
    Port (clk_in: in std_logic;
    the_input: in...
  22. [SOLVED]Closed: Conversion of std_logic to integer in VHDL

    Hi,
    I know this topic is being discussed earlier, but I think my issue is little different.
    Here is my test code:


    -----------------------------------------------------------------------------...
  23. [SOLVED]Closed: Re: VIVADO .SRCS folder disappeared, even in new projects

    Yes, and thanks.
    But is there any way I can restore the .srcs folder back in working directory, as .srcs folder is invisible and project files are appearing on desktop.
    Even in the new projects,...
  24. [SOLVED]Closed: VIVADO .SRCS folder disappeared, even in new projects

    Hi,
    I was working with my Vivado project, suddenly something happened and .srcs folder vanished. Although the project files are still visible in Sources pan of Vivado. File are still working, even...
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    Closed: Re: Registers in FPGA fabric

    This will be integrated in Labview.
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