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Type: Posts; User: dave_59

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    Closed: Re: default statement in case

    The default case branch is there to prevent your FSM from locking up unto an unspecified state. In simulation, this can happen when X's get into your state variable. For synthesis, you want your FSM...
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    Closed: Re: Testbench input stimulus

    You may have race conditions if your module also has code that waits for @(posedge clock). The same rules apply between your testbench and module as well as module to module. Use non-clocking...
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    Closed: Re: parameterized insertion of bits to data

    I don't understand either.
    Please show an example with sample data input and output values. How is control used? What order to the bits in append_data get selected? What happens when bits_to_append...
  4. Closed: Re: Alternative of “can not set both range and type on function declaration” in veril

    Remove the reg keyword in the function return.
  5. Closed: Re: Req: Bluspec Systemverilog good learning materials

    http://wiki.bluespec.com
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    Closed: Re: Beginning and end of a time step

    You are missing the code that changes clk and in. And nothing changes at the end of a time step. Change has to happen first, and only when there are no more changes can you proceed to the end of the...
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    Closed: Re: Beginning and end of a time step

    You have to look at how every signal changes value. Assuming every signal that changes on a clock edge uses a non-blocking assignment, there will be no race conditions. And you may have to look...
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    Closed: Re: Beginning and end of a time step

    If you use blocking assignments to a and b, you have a race condition. That is the whole point of using non-blocking assignments when one always process writes, and another always process reads the...
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    Closed: Re: Beginning and end of a time step

    This is not the correct way of thinking about it. The RHS of non-blocking assignment gets evaluated as soon as the previous statement completes. The LHS c gets scheduled to update after in another...
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    [SOLVED]Closed: Re: $urandom_range is generating same values

    That is the correct behavior - it's called random stability which allows you to debug your test should it fail. You need to change the initial seed if you want another set of random values. Using...
  11. Closed: Re: Verilog wire vs reg. Which one should I use and when / why?

    Please see http://go.mentor.com/wire-vs-reg
  12. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    The `` and `" are SystemVerilog token pasting operator. Normally, the macro pre-processor only works with inseparable tokens like identifiers, numbers and strings. If you want a macro argument...
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    Closed: Re: System verilog, fork join_any

    You will need to use a semaphore

    semaphore s;

    s = new(0);
    fork
    begin : process1
    ...
    s.put(1);
    end
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    Closed: Re: blocking assignment in always_comb

    Assuming the missing begin/end was a typo, they are functionally equivalent and should synthesize to the same hardware. The only difference is in simulation debugging, you'll be able to see the...
  15. Closed: Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

    There are still some applications where traditional logic synthesis tools do not produce optimal results, so other means must be used. Sometime people do draw schematics by hand, or have scripts that...
  16. Closed: Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

    Just to correct ThisIsNotSam's answer, one can take a nettist of gate/switch-level primitives and feed it to an IC layout tool.
  17. Closed: Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

    All major simulation tools support Verilog switch-level primitives. People who design FPGAs (not the users who program them) may utilize switch level primitives, especially in the simulation of the...
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    Closed: Re: Writing ModelSim do files

    ModelSim uses standard TCL.

    But, DO NOT write your stimulus that way. Use the same language you wrote your design with. And you are not restricted to synthesizable coding rules.
  19. Closed: Re: what $finish will be sythesis to in verilog?

    The circuitry to do this goes beyond what you could describe in plain digital Verilog. Power is analog,
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    Re: Bluetooth connection with a smartphone?

    This was my first hit when I searched for "FPGA development boards with bluetooth"

    https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards
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    Closed: Re: Verilog Assignment with condition

    If there is clear execution ordering of a set of nonblocking assignments, the order of the resulting updates to the LHS are preserved. So the second assignment overrides the first.

    In synthesis,...
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    Closed: Re: Automatize simulations in Modelsim

    You want

    vsim -batch -do myScript.do <args>

    This is quicker than -c as it doesn't invoke an interactive Tcl shell
  23. Closed: Re: How to generate the vcd file in modelsim for power estimation using PrimeTime Px

    You should be using SAIF format instead of VCD format for dumping. It's much more compact.
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    Closed: Re: SerDes - architecture and applications

    The bottom of the Wikipedia page you reference links to many applications. Most common are applications that communicate over a differential pair(Ethernet, LDVS), or radio transmission.
  25. Closed: Re: Using different time units in Verilog simulation

    SystemVerilog allows time units.
    x <= 0;
    x <= #2ns 1;
    x <= #4ms 0;
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