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    Closed: Re: parameterized insertion of bits to data

    I think the output is 4*InputWidth + 4*bits_to_append in width. If this is the case, the locations of the added bits is known and easy to calculate.
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    Closed: Re: I2C not working properly

    I agree with changing the input to something that has hysteresis. Also, if you keep this test circuit you should have some way to debug it better. It sounds like you are trying to infer internal...
  3. Closed: Re: Facing some error in Verilog HDL coding of Standard deviation calculation?

    looks like you have clog/pow declared in a header which is included before the module. Verilog doesn't allow this and the functions are ignored. Using these incorrectly declared functions in a...
  4. Closed: Re: Real time voice encryption/decryption with FPGA

    how do you send data to the receiver? can you make changes to how you send data to the receiver?
  5. Closed: Re: Real time voice encryption/decryption with FPGA

    If blind decryption is needed, and if the AES mode allows, it should be possible to estimate which of the 128 different bit alignments is correct. decryption failures look like noise while success...
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    Closed: Re: Transferring data from PS to PL

    IIRC PS-PL is mainly for control/status -- lower rate stuff. I think the normal flow is for the PL to take general commands from the PS, provide updates to the PS, and sometimes access PS memory.
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    Closed: Re: verilog code needed for my sequence

    use either the shift operator "x <= x >> 1;" or concat "x <= {1'b0, x[0:62]};" or be lazy "x <= x[0:62]". division should also work "x <= x/2" but will annoy more people.
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    Closed: Re: How to instantiate a submodule in Verilog

    is "sine8192.hex" something that works in simulation? I suspect readmemh failure is just a warning or silent failure.

    IIRC the last time I used readmemh with quartus I needed to add a sanity...
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    Closed: Re: How to instantiate a submodule in Verilog

    It's tricky. best to read the docs for whatever synthesis tool you're using. More reliable than people guessing. You may also be expecting too much, sadly.
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    Closed: Re: How to instantiate a submodule in Verilog

    inferring rams/roms still can be a tricky subject. you should read the synthesis coding guide and also look at the logs and implementation results. seemingly minor details can cause the tools to do...
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    Closed: Re: How to instantiate a submodule in Verilog

    I test different code styles. There is a style that uses tasks/functions to make complex code shorter. I had mixed results -- the code intent was clear but the tasks had to be written in a specific...
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    Closed: Re: Injecting errors in SystemVerilog

    depends on the application. for something like hamming code with reasonable bus widths you can just have a N**2 loop where data = data ^ ((1<<i) | (1<<j)). and i,j can be one higher than the bus...
  13. Closed: Re: Verilog: read 2 values from an array at the same time.

    I expect the tools to implement your table in BRAM. This is desirable in this case. You should confirm this in synthesis logs -- the tools sometimes do unexpected things.
  14. Closed: Re: Verilog: read 2 values from an array at the same time.

    @Pastel: DMEM/BRAM are Xilinx's names for "distributed memory" and "block ram". Intel also has similar blocks. BRAM requires 1+ cycle of read/write latency but is the most dense. DMEM allows...
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    Closed: Re: UART Transmitter by FPGA

    index/count are variables local to each process. index/count in the first process are never used but are assigned. The are different from index/count declared in the second process.

    The need to...
  16. Closed: Re: Verilog: read 2 values from an array at the same time.

    You can synthesize arrays with many/multiple accesses. The tools will do something to make them work. In some cases this means using a dual-port BRAM/DMEM primitive. In some cases it means...
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    Closed: Re: How to instantiate a submodule in Verilog

    I know I've seen this. I think some code generators will do this for convenience. I know I've seen people put short testbenches in the same file. I'm pretty accepting of that because the...
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    Closed: Re: Advanced VHDL book recommendation

    Having next_state does allow the register to be cleanly defined.

    Your changes to the code sample do work. In some styles it can be confusing/annoying/verbose. The logic for a signal that matters...
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    Closed: Re: Advanced VHDL book recommendation

    I agree that logic should be registered where possible and latches should be avoided. That is a different argument.
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    Closed: Re: Advanced VHDL book recommendation

    That is a good example of why one-process is dangerous. There is a comment "output is a function of the current state only". This is wrong -- there is an extra register stage. Is this an error? ...
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    Closed: Re: Advanced VHDL book recommendation

    IIRC, it was from 1999. The style that it was trying to replace was the style where every signal is in its own process. Some of the arguments make way more sense if you compare them against common...
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    Closed: Re: Advanced VHDL book recommendation

    I like a compromise style where the fsm state transition logic is written as two process and outputs (and usually counters) are written as one clocked process. Having next_state is almost always...
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    Closed: Re: Advanced VHDL book recommendation

    I don't think there are any really good coding style guides. The languages are overly sim based to the point the coding for synthesis is dangerously affected. Guides are often based on capricious...
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    Closed: Re: I/O banks in an FPGA. Is it important for routing?

    It can affect the pcb layout. It also makes higher performance busses more difficult. Beyond any specialized resources that are local to a io-bank, it also can lead to timing errors. The tools...
  25. Closed: Re: Verilog wire vs reg. Which one should I use and when / why?

    I suspect this might just mean that you could write code in always blocks that the synthesis tool won't synthesize. For example, tools will not synthesize while loops except in very specific cases. ...
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