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Type: Posts; User: ThisIsNotSam

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  1. Closed: Re: Convert ITF file to ict for captable generation

    It is yellow and has some little pink dots on the back.

    Joking aside, it's a linux binary. It doesn't need an extension.
  2. Closed: Re: Convert ITF file to ict for captable generation

    there is a utility that converts, these are not commands. check if it is present in your cadence installation folder.
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    Closed: Re: Protocol Design - System Verilog

    OCP, as far as my impression of the industry goes, is a dead technology. Maybe OP could try AXI, SPI, etc.
  4. Closed: Re: How to install and use Standard Cell Library in Virtuoso?

    Nope. You need a GDS or an extracted netlist. Looks like you have neither.
  5. Closed: Re: How to install and use Standard Cell Library in Virtuoso?

    Who said you are supposed to do that? digital designers rarely work at that level. That's why the front end views is sufficient for them most of the time.
  6. Closed: Re: How to install and use Standard Cell Library in Virtuoso?

    you don't 'install' anything into virtuoso environment, you import a library. you can do it with GDS files which I assume are in the physical compiler folder. It's also possible you only got access...
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    Closed: Re: Max tran, max cap ,max fanout

    max cap and max fanout are a consequence of the technology. usually a designer will not play with those values.
    max tran is a combination of technology characteristics and design goals. I tell my...
  8. Closed: Re: GLS with a Timing Model using PrimeTime and Modelsim

    When using SDF files, designers always make the same two mistakes:
    - generate empty files and then wonder why it doesn't work
    - generate a valid file but with hierarchy mismatch. this happens...
  9. Closed: Re: How to instantiate a submodule in Verilog

    I have not seen that coding style in any of the companies I have worked for, taught for, or consulted for. Never allowed. My experience of 1, of course.
  10. Closed: Re: How to instantiate a submodule in Verilog

    From my 10 second glance at the code, it looks like you are not breaking up the code into multiple files. different modules go into different files, that simple. keep the testbench stuff separated...
  11. Closed: Re: How to pass arguments to PrimeTime TCL script? (using pt_shell -file myScript.tc

    it's probably easier to set environment variables in your linux system and use those in the script
  12. Closed: Re: Can't Read SAED32nm libraries for design compiler

    I think now there is an issue with your script other than finding the files. It looks like each std cell is an individual design, which is wrong. But then again, I don't use DC that often. Maybe...
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    Closed: Re: PCB designing and wire bonding both

    I would suggest using a socket instead of wire bonding to the PCB. That's how I do bring up tests, at least. Production is a different beast, you don't want to use a socket for that.
  14. Closed: Re: Can't Read SAED32nm libraries for design compiler

    step 1) stop using all these libraries and add them one by one
    step 2) stop using relative paths and use absolute paths
  15. Closed: Re: In PrimeTime, how can I view setup/hold times per endpoint in easy format for par

    I am not a primetime user but I found the answer through goggle in a couple of clicks:
    set x [get_timing_paths -from A -through B -to C]

    Come on man...
  16. Closed: Re: how to design combinational parts of benchmark circuits

    Please don't write code at this level. this is called structural verilog and it is essentially the same as putting a schematic together. This type of effort has no place in today's EDA industry. You...
  17. Closed: Re: Coupled nets from parasitics spef file

    I am not sure I understand the question. If you are asking if C is counted twice, the answer is yes. You have A->B and B->A listed as being separate capacitances with the same value.
  18. Closed: Re: In PrimeTime, how can I view setup/hold times per endpoint in easy format for par

    There are a million ways you can parse the reports with external tools. Writing a python parser is so easy these days.

    Another alternative is to learn TCL, which will come in handy in so many IC...
  19. Closed: Re: GPU with general purpose operating system

    Sadly enough, I know exactly what the term is and remember studying it in computer architecture 101.
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    Closed: Re: Deciding orientation in IO cells

    What do you mean decide orientation?! If the cell is on the left or right of the chip, it must be horizontal. if the cell is on the bottom or top, it must be vertical. this is so trivial, just think...
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    Closed: Re: CRC Error insertion and detection

    it's probably easier to have two instances of the design, one that you insert errors and one that you don't. provide the same inputs and see if the outputs match.
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    Closed: Re: CRC Error insertion and detection

    you can use the force command in the simulator or the verilog version of force
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    Closed: Re: Mixed Signal IC Grounds

    Don't forget that your planning still has to respect whatever constraints that come with the package and the IO cells. I have often seen packages and IO rings that short all grounds together, so it...
  24. Closed: Re: What if fin width of finfet will adjust..

    Fin width cannot change, at least not in the 5 FinFET technologies I have had access to. You have to understand that process engineers spent years optimizing the process for that specific width, this...
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    Closed: Re: Verilog Coding in Cadence Vertuoso

    These are very basic issues. I suggest you talk to the instructor/professor/TA of your course. Perhaps even a friend with some knowledge of linux can be of assistance.
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