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Type: Posts; User: Chinmaye

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  1. Closed: Re: Convert ITF file to ict for captable generation

    Sir, What is a linux binary file? Could you please explain more on this? Also is it possible to create layouts in innovus, without using captable files?
  2. Closed: Re: Convert ITF file to ict for captable generation

    How does the utility look like? Does it have any extension?
  3. Closed: Convert ITF file to ict for captable generation

    Dear all,
    I want to convert itf file to ict file and use it for captabl generation. How can it be done?
    The following link provides commands to do it. But again i do not understand that....
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    Closed: Very accurate analog comparators

    Any leads on how to go about building an analog comparator that can detect signals even with 20mV difference?
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    Closed: Re: Saving the layout in innovus

    Thank you sir. I was able to generate the gds file using the command stream out. But when i use the same .gds file to generate layout in virtuoso, there are lots of missing layers and it looks...
  6. Closed: Re: what is the bandwidth achieved for the given configurations

    For s single stage, Gain * Bandwidth product is constant. Gain of triple cascode >cascode > common source. Hence Bandwidth of Common source > cascode> triple cascode
  7. Closed: Re: MOSFET linear and saturation region operation

    MOSFET behaves like a resistor in linear region with resistance = 1/(un*cox*(W/L)*(Vgs - Vth)) for small values of Vds.
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    Closed: Re: Saving the layout in innovus

    Yes sir. The log file does not show any error. Attaching the log file for reference. Could you please let me know if there are any commands that can be run to get the gds file instead of GUI?
  9. [SOLVED]Closed: Re: Error during clock tree synthesis in innovus

    This problem automatically got solved when i run nanoRoute command
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    Closed: Re: Saving the layout in innovus

    I am trying the option save-> gdsii. But cannot find a gds file in any folder. I am attaching the screenshot of the steps i am following to get gds file. Please let me know what i am missing. Plz...
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    Closed: Saving the layout in innovus

    Dear all,
    I have generated a layout in innovus for a sequential circuit. I have run all the steps including routing. Now i would like to save the layout and would like to access it again further. I...
  12. [SOLVED]Closed: Error during clock tree synthesis in innovus

    Dear all,
    I am new to innovus tool. I get this error during clock tree synthesis.
    ERROR: (IMPCCOPT-2215): The route/traversal graph for net 'clk' is not fully connected
    What does it mean and how...
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    Closed: Re: Help in understanding innovus

    Sir,
    What does max tran mean? What is the nominal value of that?
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    Closed: Help in understanding innovus

    Dear all,
    I am new to innovus tool. I have attached the timing report taken after placing my standard cell. I would like to understand a few things in the report. What does TNS = 0 mean? What does...
  15. [SOLVED]Closed: Re: Timing slack showing Unconstrained after synthesis in genus

    Yes. That was a sample file that i used. it works with my other programs that has one module. Here i am using structural model and that is what i am not sure about.
  16. [SOLVED]Closed: Timing slack showing Unconstrained after synthesis in genus

    Dear all,
    I am trying to synthesis my verilog code to check the slack. But the timing slack shows unconstrained. Attaching the declarations in my top module and constraints file.
    154202
    154203
  17. Closed: multiply -ve number and a fraction in verilog

    Is it possible to multiply a negative number with a fraction in verilog? Eg :- -1*0.1;
    If yes how can it be done? What is the format in which the result is stored?
    TIA
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    Closed: Re: Critical path while using xilinx ise

    Where do i check that? In the synthesis report right?
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    Closed: Critical path while using xilinx ise

    Dear all,
    When i tried to synthesize my verilog code in ISE, my timing report said,

    Minimum period: 4.490ns (Maximum Frequency: 222.712MHz)
    Minimum input arrival time before clock: 4.358ns
    ...
  20. Closed: Re: Generate random sequence of 1's and -1's in matlab

    This doesnt always give a mean of zero
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    Closed: Loop bandwidth of a Charge pump PLL

    Dear all,
    I am new to PLLs and I have been trying to study it from Razavi. I am confused with what the loop bandwidth in charge pump PLL mean? Does it mean wn in the second order system? or Zwn is...
  22. Closed: Solution manual RF Microelectronics by razavi

    Dear all,
    I am looking for solution manual of RF Microelectronics circuits by razavi. Any leads?
  23. Closed: calculating corner frequencies for oscillators

    Dear all,
    I have designed a n LC oscillator and simulated it in cadence. I have also plotted its phase noise vs frequency after PSS and Pnoise analysis. How do i find what exactly is 1/f2 and 1/f3...
  24. Closed: Cross coupled LC oscillator design current saturates but voltage doesnt

    Dear all,
    I am new to oscillators and trying to understand it by studying from the Razavi text book. While studying cross coupled LC oscillators, i came across this current waveform which saturates...
  25. Closed: Re: Self biased inverter design with large resistor connected across it

    Yes. The noise is from feedback network itself. When i try to increase the amplitude of the output, the phase noise is affected and vice versa.
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