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Type: Posts; User: niciki

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  1. [SOLVED]Closed: Re: Can you help me with this Verilog to VHDL translation?

    What tool do you use for synthesis? Does it support both languages? If so, then you can instantiate Verilog modules inside VHDL wrappers and vice versa.
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    Closed: Re: VHDL code flow in ISE Design Suite 14.7

    What are your constraints about output ports?
    DRIVE constraint may help you. For more information look for it in the Constraints Guide for ISE:


    INST “instance_name” DRIVE= { 2 | 4 | 6 | 8 | 12...
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    [SOLVED]Closed: Re: VHDL Counter FPGA Spartan-6

    Your led will be '1' only for ONE! clk cycle when "count = 250000000-1", otherwise it's '0' for rest of the time (I guess your eyes wouldn't see the effect).
    Change the line 26 to toggle led signal:...
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    Closed: Re: FPGA neural network training

    You did a Raspberry Pi 3 B+ project with some camera module. I suggest to use the same camera and describe the camera controller inside FPGA. Maybe FPGA project already exist in the Internet for your...
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    Closed: Re: FPGA neural network training

    Please consider the following:
    * You want to transfer image pixels to FPGA - how many pixels per image and what is a size of an image? Can you transfer only a bunch of pixels at a time that can be...
  6. Closed: Re: Spartan 6 - OSERDES2 to ODDR - Unroutable signals

    Have you checked ug381?
    There is a following drawing which might give you a hint:
    150741

    The ODDR is after 3rd OSERDES(counting 4th -> 3rd -> ODDR).
    Make sure you didn't instantiated the 2nd...
  7. Closed: Re: Help to get Answer in VHDL code for use Floting point and RAM

    You should delay the write to the RAM until the floating point IP would have the valid value at the output.
    Figure out why you have X'es in the simulation.
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    Closed: Re: TKEEP and TSTRB in AXI Stream

    In that situation binding TKEEP to all 1's will work.

    I would suggest to check your vendor specification about the IP and AXI-Stream protocol, because e.g. Xilinx in UG1037 at page 100 gives clear...
  9. Closed: Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    When you use AXI DMA to transfer data from Zynq to DDR, then you would get: Stream (Zynq) => Memory Mapped (DDR).
    When you transfer data from DDR to Zynq, then you would get: Memory Mapped (DDR) =>...
  10. Closed: Re: Transfer Data from DDR3-PL to BRAM using Zynq on ZC706

    I suggest to break the problem into smaller parts.
    In SDK you can find the Memory Test Application (next to Hello World app) that finds memory components in your design and performs read/write...
  11. Closed: Re: clocking issues in capturing debug signals in ILA

    Group every probed signal based on its clock domain. Use as many ILAs as you have clock domains i.e. connect the probed signals and clock from one clock domain to one ILA.
  12. Thread:

    by niciki
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    Closed: Re: hardware(rtl)/software co-simulation

    Check QEMU if it suits your need.
  13. Closed: Re: [MOVED] Why FPGAs are shipped with optional microcontrollers soft cores

    Just consider what is the microcontroller in general - consider it as a sequential block just like specific state machine. That state machine considered as the microcontroler can be easily changed by...
  14. Closed: Re: Microblaze and PmodCAN (Digilent IP core) in Vivado 2018.2

    What the Tcl console in Vivado says? Is there any errors during instantiating the PMOD ccomponent?
    Please copy the content here for analysis.
  15. Closed: Re: Microblaze and PmodCAN (Digilent IP core) in Vivado 2018.2

    It looks like you don't have some definitions in board file or the interface definition is missing in you Vivado project.

    Check if you have added interface definition...
  16. Closed: Re: Microblaze and PmodCAN (Digilent IP core) in Vivado 2018.2

    Isn't it 10-pin Pmod Interface Type 2A (expanded SPI) plus GND and VCC described here https://reference.digilentinc.com/_media/reference/pmod/pmod-interface-specification-1_1_0.pdf?

    You have 10...
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    Closed: Re: VHDL "library" and "use.all" clause

    Then you would use:


    Inst : entity x.some_entity
    Port map (
  18. Closed: Re: How to perform Flash Programming of the ZC706 with our own design files and bitst

    You need to analyze every partition one by one and it depends.

    Assuming that you always use ZC706 board and Linux then:
    * FSBL can be unchanged;
    * Bitstream can be unchanged only if PL part is...
  19. Closed: Re: How to perform Flash Programming of the ZC706 with our own design files and bitst

    From UG1046 (U-Boot chapter) and UG821 (Figure 3-15: Zynq-7000 AP SoC Example Linux Boot Image Partitions) we have the proper boot image partitions sequence for Linux (according point 4 from post...
  20. Closed: Re: How to perform Flash Programming of the ZC706 with our own design files and bitst

    Please show the printscreens with steps and the printsceen when it fails showing the ERROR message.
  21. Closed: Re: How to perform Flash Programming of the ZC706 with our own design files and bitst

    Have you read this: https://forums.xilinx.com/t5/Evaluation-Boards/Flash-Programming-in-ZC706/td-p/848672 ?
  22. Closed: Re: In ZYNQ FPGA : Who is controlling the AXI Memory-Mapped to PCI Express module? Th

    The AXI Memory-Mapped to PCI Express module has AXI-Lite interface to control registers and AXI-Full interface for data. It is up to you what module will be connected with both interfaces. It can be...
  23. Closed: Re: Unable to grab PCIe ref_clk for the axi_pcie in ZC706 board !

    I have some experience in creating the board, pins and preset files (XML files).
    My first fought is to install latest Vivado 2018.2.1 (even if you don't have a license) and check if the board...
  24. Closed: Re: Converting a RF signal into baseband using VHDL

    Look for "digital IQ demodulator".
    In short the understanding of the following is needed:
    * complex signal
    * complex sinusoid
    * spectrum shifting
    * equivalence between convolution in time domain...
  25. Closed: Re: How do i design a schematic for Counter with Reset/Pause on FPGA

    Start from drawing your design and every component on the paper. You don't need to know VHDL to do so.
    Then draw the design in the schematic and simulate the design.
    With which part of the...
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