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Type: Posts; User: vivekroy

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  1. Closed: Re: How to calculate bandwidth for this circuit, including lower and higher cut off f

    But doesn't this look like a stacked power amplifier? Do we need to care about open loop stability of a power amplifier? If we can get rid of the feedforward impedance, then for passive terminations,...
  2. Closed: Re: Problem in plotting I/O waveform in Cadence

    Use the delay function to plot the delay between the two wave-forms and then do a Y vs Y plot.
    Alternatively you can save both your voltage/current/charge waveform and your delay waveform in csv...
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    Closed: Re: Verilog-a code to latch analog voltages

    Here you go


    // VerilogA code

    `include "constants.vams"
    `include "disciplines.vams"

    module veriloga_latch(vin,vclk,vout_sampled);
    input vin,vclk;
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    Closed: Re: Verilog-a code to latch analog voltages

    Look at page 113 of http://www.lumerink.com/docs/VerilogA.pdf

    Your exact solution is given!!
  5. Closed: Re: Problem in plotting I/O waveform in Cadence

    Connect a capacitor to your charge pump output. Make sure its large enough so that when the CP turn on, the voltage does not change too much.

    Start with two vpulse sources that have a phase...
  6. Closed: Re: In PA, if the bias is VDD then how can swing be 2*VDD with inductive load

    You have the explanation there.

    If you want more insight into such behavior, refer to "Pulse, Digital and Switching Waveform" by Millman and Taub.
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    Closed: Changing the 'VDD' and 'VSS' value in CppSim

    By default most digital blocks in CppSim have an output between -1 and 1. I want it to be between an user-defined fixed set of values, for eg. 0 and 1.8. Till now I have been using a multiplier...
  8. Closed: Re: Help on Ocean scripting: run one analysis and use that results in another

    I don't like using calcVal in global variables. I always prefer using it in local variables. (Make sure to disable the global variables by unchecking the box next to the respective global variable)
  9. Closed: Re: Help on Ocean scripting: run one analysis and use that results in another

    Yeah, it is not a calculator function.

    I think maybe the SKILL Language Reference Manual?

    Or maybe in the SKILL API Finder which can be invoked from the Virtuoso CIW Window.
  10. Closed: Re: Help on Ocean scripting: run one analysis and use that results in another

    I did not follow the question. The design variable for your second analysis is a result of the first analysis?

    If that is the case, then split your simulation into two different simulations and...
  11. Closed: Re: How does this OTA operate with very low voltages

    This is what I think (and I maybe wrong)..

    Your input pair will continue to work in saturation as long as the drain voltage (== Vgs of nMOS diode) does not exceed the threshold voltage of the...
  12. Closed: Re: How do you choose input power while doing loadpull?

    Why not put in the frequency everywhere as a variable and do a parametric sweep of that variable.
  13. Closed: Re: How to realize inductor from transmission line (micro-strip and CPW lines)

    CPW stands for co-planar waveguides. Transmission lines can be realized on-chip using co-planar metals as Ground-Signal-Ground configuration. It can also be realized by routing the signal trace on a...
  14. Closed: Re: Inverters as Level Shifter with HVT and LVT transistors

    A CMOS inverter has no static power consumption. When input is high, the Vsg across PMOS = 0; no PMOS drain current. When input is low, Vgs across NMOS =0 ; no NMOS drain current.
    In your case,...
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    Closed: Re: CMRR at different closed loop gain

    Does the closed loop gain change with your feedback network? If it does (for example due to loading), then theoretically, CMRR by definition changes.
  16. Closed: Re: Inverters as Level Shifter with HVT and LVT transistors

    Static power consumption when input is high.
    When your input is high, there is a |Vgs| = 0.8V which will cause leakage current to flow. When your input is 0, the NMOS is turned off and there is no...
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    Closed: Re: Sooch current mirror

    I can't speak for other designers but whenever I had some extra voltage headroom, I used to use it in the reference current sources. The bias current typically comes from a bandgap and it needs to be...
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    Closed: Re: Sooch current mirror

    I tried this circuit once in 28nm. The issue I faced was that the resistor variation was too much for my application. Extreme corners of MOS needs to be combined with the extreme corner of resistor...
  19. Closed: Re: How should be Pin1dB less or more compared with Pout1dB?

    Of course you need to consider that. Your measurement equipment can only deliver a maximum amount of power without itself compressing. If you do not have enough gain, then you cascade the stages to...
  20. Closed: Re: LNA with degenerated inductor - Where does the power go?

    I maybe wrong but this is how I would interpret this result.
    The following is an excerpt from Razavi's RF microelectronics:
    155220
    The expression that you mentioned is derived under the condition...
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    Closed: Re: Power Amplifier Design

    I do loadpull for the main amplifier at two points:
    1. Just before the peaking amplifier turns on and begins to significantly do "load modulation".
    2. When both the amplifiers are saturated.
    For...
  22. Closed: Re: How to increase high frequency output power

    The curve that circuitking has shared shows a very wide region of operation. Obtaining matching across such a wide range is quiet difficult. Typically, it would require the matching circuits to be...
  23. Closed: Re: How to increase high frequency output power

    Can you maybe elaborate on what you mean by "high frequency output power"? If you are referring to higher power at high frequency, then inductive peaking will not help (and of course you won't get...
  24. Closed: Re: Using VCVS as delay elements result in period signal rising and falling time chan

    Have you tried changing the maxstep parameter in your transient simulation?
  25. Closed: Re: Stability of a circuit and its role in design steps

    I know its not relevant to this thread particularly, but it is particularly relevant to HB not converging for conditionally stable circuits.

    I was once designing a PA using bipolar devices at...
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