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Type: Posts; User: BigKuma

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  1. Closed: Re: Timing and routing to large number of memory banks

    The signals from router to the memories are all separate and registered.
    Even in the timing report, I see only two entries in the path, WR_ADDR_REG(my signal) and asyncram address register.
    ...
  2. Closed: Timing and routing to large number of memory banks

    I am using Quartus and Stratix V.

    I have a design that has 14 memory banks. Each bank is 64xM20K blocks.

    There is block (MUX) that reads/writes one bank, while another block (FFT) that...
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