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Type: Posts; User: kangalooj

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  1. Closed: JESD204B with two different device clocks

    Is there any chance to make JESD204B works with FPGA hava different device clock than ADC but share same sysref and sync clocks?
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    Closed: Re: Designing SDR Platform

    I have designed SDR (Software Defined Radio) that works with PC (and only PC with Windows because my SDR written in C#!). My SDR produce signal samples (16bit I/Q with 8MSPS rate) that I need...
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    Closed: Re: Designing SDR Platform

    My SDR must feed the signal generator! I want to generate samples in my SDR and transfer it to DAC via PCI-Express.
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    942

    Closed: Designing SDR Platform

    I need to generate a signal have 16-bits samples (I and Q each 16bits) with 8 MSps sample rate, to use with my SDR (Software Defined Radio).

    I want to generate signals on the fly, so I can't store...
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