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    [SOLVED]Closed: Re: digital integrated circuits

    Yep. In a modern ASIC there is still a lot more. You can expect a lot of level shifting going around, a lot of clamps for ESD protection, buffers, etc.
  2. Closed: Re: Is it necessary to set FPGA and ASIC operating frequency to the same amount?

    There is no clear rule on how to convert the max clock frequency of an FPGA implementation to an ASIC implementation. Play with the synthesis tool, try some higher values and see what you get. There...
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    Closed: Re: max_transition Violation

    Maybe neither, maybe both. max_tran violations may indicate some issue in the sdc files, may indicate issues with library characterization, may indicate poor synthesis. You have to look at it case by...
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    Closed: Re: Synopsys DC: Tracing clock path

    Do you mean visualize the clock tree? It is not implemented during logic synthesis, only later in physical synthesis. I have a feeling you are looking for something that isn't there yet.
  5. Closed: Re: What are the meaings of the following Calibre warnings

    Assuming you are using calibre for DRC, these errors happen when you generate broken GDS. Maybe the reason is a library is missing, maybe the reasons is two libraries have cells with the same name.
  6. [SOLVED]Closed: Re: [moved] What is Cadence genus synthesis, report power?

    you must have set the clock somewhere in your synthesis script or through an external sdc file. check what value you have used. dynamic power is a function of the clock frequency, no doubt about it.
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    Closed: Re: What is Negative timing checks

    $setuphold is just verilog terminology for the timing check task. it can trigger for either reason. when it triggers, it will tell you which one was violated. just check the console/logs.

    I am not...
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    Closed: Re: SiliconSmart pin and lib file

    I assume you are characterizing a flop. You need to capture clk-->Q delays and setup/hold times. You need to follow the templates for flops, there is a specific syntax for passing a table of inputs...
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    Closed: Re: Logic duplication and optimization

    agree 100% with the posters above. if you want to do manual optimizations, it's better if you think a level above (i.e., pipelining and architecture options). this is really where your coding...
  10. Closed: Re: Relxpert model file which supports UMC65 for reliability simulation

    No one can send you such file, it would be a gross violation of NDA. You have to get the file from the foundry.
  11. Closed: Re: CMOS ring oscillator frequency degradation through years

    Not sure what the issue is. The tools don't know how to calculate aging, they take values from the spice model of the transistors. if you are using the same transistor model, I would expect the same...
  12. Closed: Re: Voltage drop of on die power gating cells

    Yes, it usually is a big transistor on the header and another big one on the footer. There is a drop, but this usually is well within the characterization range of the standard cells. Say, for...
  13. [SOLVED]Closed: Re: Preventing using a certain cell in cadence encounter

    from being placed or from being instantiated? different questions, different answers. I think you are looking for the set_dont_use command.
  14. Closed: Re: Voltage drop of on die power gating cells

    Not sure I understand the question. Are you implying that power gate cells will deliver a derated VDD to the block that they switch off and therefore timing analysis should take that into account?
  15. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    Exactly, I would call it Cload, not Cpar. But at this point we don't know what OP has in mind...
  16. Closed: Re: How to measure the C parasitic (internal capacitance) of an inverter using Spectr

    let me play devil's advocate here... I think OP is trying to determine the Cload seen by the first inverter by simulation means. Just a wild guess.
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    Closed: Re: Transient Simulation in Cadence

    So many silly things could have happened... maybe your GUI only lets you see 19ms and cuts off after that
    Maybe the simulation output file became too big and got cut halfway. Check the logs.
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    Closed: Re: LBIST low test coverage

    was there a question in this thread at all?
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    Closed: Re: LBIST low test coverage

    Maybe you have a very specific test case in mind? I don't agree with the assertion that LBIST is always low. Or always high, for what is worth. LBIST fits some circuits, doesn't fit others. Good luck...
  20. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    extraction tools have some expectations regarding VDD/VSS pins and how they should be named. it is possible the tool is expecting vdd! and you called VDD, or whatever other combination of. check your...
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    Closed: Re: How to fix unclocked register?

    more details needed. which tool is saying this and at what stage. what does your design look like. etc.
  22. Closed: Re: Can IP(Intellectual Property) open source, what does good business model?

    open hardware and open EDA initiatives exist for decades now... but I am not aware of any success story worth mentioning. VHDL is a good one, but it is not IP per se. opencores is a nice repository,...
  23. Closed: Re: How to choose a good university for electronics engineering in USA?

    don't forget tuition. you might be looking at 200k debt after two years of study in the US.
  24. Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    Agreed. The effects are wild, the layout is not. That was my point.
  25. Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    there is nothing special about a FinFET transistor. You have less flexibility than in older technologies. You will never draw a fin, for instance. It is always there, it is gridded and always...
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