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Type: Posts; User: dpaul

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  1. Closed: Re: Facing some error in Verilog HDL coding of Standard deviation calculation?

    All Verilog constructs should work within a file marked .sv. But the opposite is not true.
  2. Closed: Re: Implementation of a MUX for selecting from 2 different sets of inputs

    Sounds like a stages of MUXes......
    As others have pointed out, a diagram is needed.
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    Closed: Re: HELP ME the newbie with Verilog Code

    This is a very common university homework and is not difficult.
    Show us what you have attempted to do so far.
    If you are not comfortable with Verilog, then learn it first. This task will exercise...
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    Closed: Re: Using multilayer AHB-Lite

    Correct.
    There are many types of arbitration schemes that can be employed and each one has its own complexity + merits/demerits.
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    Closed: Re: Using multilayer AHB-Lite

    In my opinion a multi-layer AHB-Lite is not often employed.
    As I see it, for each layer of AHB-Lite there will be a master. And these masters should also remain connected.
    So why not directly have...
  6. Closed: Re: Shifting control from one module to another iteratively

    I think this thread is somehow related to this post:
    https://www.edaboard.com/showthread.php?386251-SystemVerilog-Input-generation

    Dear OP, I am not sure regarding your understanding of modules,...
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    Closed: Re: SystemVerilog Input generation

    Dear OP, stop all those verbose and post your TB RTL if your really want to be helped.
  8. Closed: Re: please can somebody help me, where in cpu to connect the keyboard (FPGA)

    I am giving my comments solely on the basis of the diagrams you have posting, without understanding the functionality.
    I think the correct one is in post #8 pic 1 (so it is a 3:1 MUX again),...
  9. Closed: Re: please can somebody help me, where in cpu to connect the keyboard (FPGA)

    Apologies, I had missed the I2C module.
    So as there are now the keyboard, char_ram, data_mem and i2c so there are 4 data paths going in to the CPU. So use a 4:1 MUX in front of the d_f_mem input.
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    Closed: Re: SystemVerilog Input generation

    That should also not be difficult.
    For such operations just keep 2 separate always blocks in the testbench, one for incrementing counter data and other for generating error data. Once your counter...
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    Closed: Re: Transferring data from PS to PL

    If so, then your concepts should now be clear regarding data transfer....
    What I would like to do now is to send the data from the PS to the FPGA (PL, programmable logic). I have checked on internet...
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    Closed: Re: SystemVerilog Input generation

    You should keep in mind what others have suggested.


    You can have something like...
    process for 256 bits up-counter in TB --> DUT --> process for checking the DUT output/s

    What is your exact...
  13. Closed: Re: please can somebody help me, where in cpu to connect the keyboard (FPGA)

    For the data path, yes just use a 3:1 MUX. For the other signals, use as they should be connected. You have two connection diagrams, just merge them and get a combined one, where the connectivity of...
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    Closed: Re: Verifying Large ASIC

    If I am not wrong this is where FPGA prototyping for ASICs come in. As mentioned by std_match, after the top level TB does what it is intended for, an FPGA prototyping can save a lot of time.
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    Closed: Re: For doing ECO on netlist

    Well I definitely believe you.
    What change was actually done and how it was done was not discussed. It was just a casual chat, among many other talks, with someone you meet casually in the coffee...
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    Closed: Re: For doing ECO on netlist

    @not(Sam),

    In 2012 a lead engineer from an ASIC design & verification service providing company told me proudly that they have hand-edited the dft inserted netlist (because bug/s were found by the...
  17. Closed: Re: please can somebody help me, where in cpu to connect the keyboard (FPGA)

    The two pics show 2 different implementations.
    The d_f_mem is a multiplexed input from <1> keyboard or char_ram(pic1) or <2> data_mem or eeprom.


    I did not completely understand your question. ...
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    Closed: Re: For doing ECO on netlist

    I know it is very difficult and is not standard practice. But you have a difficult limitation.
    Maybe you should wait for other members to comment.
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    Closed: Re: For doing ECO on netlist

    Open the netlist using a text editor and hand-edit it (you should know what you are doing)! :-p
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    Closed: Re: Transferring data from PS to PL

    see this thread on PS-PL communication - https://forums.xilinx.com/t5/Embedded-Processor-System-Design/PS-PL-communication/td-p/847775

    You might also need:...
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    Closed: Re: Transferring data from PS to PL

    For PL to PS, you can also use the AXI i/f.
    The PS section can typically stay as the master and the PL section can stay as the AXI slave.


    The AXI master side (PS) needs to initiate a write...
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    Closed: Re: verilog code using vivado

    Post the complete RTL.
    Are you properly doing the system clock input pin assignment in the xdc file?
  23. Closed: Re: Verilog code for 8 bit register with read/write

    I hope you realize that in order to have data from an axi slave to a 8 bit register, the 8 bit register must also have an axi wrapper. That axi wrapper must act as an axi master. Since you already...
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    Closed: Re: Embedded Linux Application

    For Xilinx FPGAs containing ARM core/s I can recommend you to start with the this free to download eBook:
    http://www.zynqbook.com/

    Many of the answers you can get there.
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    [SOLVED]Closed: Re: Modelsim clock signal

    I would never use stuff as create_wave or try to force a toggle behavior in order to generate a fundamental signal such as clock.
    For signals such as clocks and resets, drive them from the...
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