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Type: Posts; User: guru2kiot

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  1. Replies
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    Closed: Re: radix-10 multiplication

    Hello ecasha,
    To learn basics of radix-10 decimal multiplication and its implementation purpose kindly see the links


    http://www.eecs.wsu.edu/~ee314/handouts/numsys.pdf
    ...
  2. Closed: Re: Good Books for Base Station Antenna Design

    Refer books like Basic Antenna Principles for Mobile Communications Peter Scholz,Antennas for Base Stations in Wireless Communications by Kwai-Man Luk and Zhi Ning Chen
  3. Closed: How to install tessent tool using linux?

    Hello,
    How to install tessent tool using linux commands? Please can anyone tell me what is the procedure to installation?
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    [SOLVED]Closed: Re: stuck at faults implementation using FPGA

    Hello dpaul,
    Thank you very much for your valuable response......above given link is surely very useful one for stuck at faults. In that discussion faults injections signals and its syntax followed...
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    [SOLVED]Closed: stuck at faults implementation using FPGA

    Hello,
    Can anyone suggest me how to implement stuck-at-faults (stuck-at-0 or stuck-at-1 faults) using FPGA. In my coding i have used stuck at faults using force the signals. Its able to done...
  6. Closed: Re: [moved] Which institute in Bangalore is good for Systemverilog & UVM

    In Bangalore you can try with sion semi or cvc pvt ltd or chipedge tech or vector india for system verilog courses
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    [SOLVED]Closed: Re: Testability Measurement Tools

    If i made any confusions means sorry to all
    i am not used any standard tools so far.....in future days i am going to access standard tools through institution.....before that my plan is searching...
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    [SOLVED]Closed: Re: Testability Measurement Tools

    if i confusing you means really sorry........

    yes my aim is to perform testability measurement by using particular circuit netlist(gate level),then by applying various faults to the circuit &...
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    [SOLVED]Closed: Re: Testability Measurement Tools

    Thank you for your reply....
    no, generating test patterns for various faults is one of my idea... my another idea is using various faults to calculate the fault coverage,point of...
  10. Closed: Re: Inductance measurement- Which is better?

    In my opinion for measuring inductance better method is
    (i) connecting a resistance in series with the inductance, thereby measuring the time constant, from which the inductance value is...
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    [SOLVED]Closed: Re: Testability Measurement Tools

    thanks for your valuable suggestion....
    I am asking what are the tools used to calculate the fault coverage,Controllability,observability measurements & estimation of test vector length???
    please...
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    [SOLVED]Closed: Re: Testability Measurement Tools

    thanks for your reply....

    yes,testability measurement means that for calculate test coverage and also Controllability,observability measures & estimation of test vector length.......
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    [SOLVED]Closed: Testability Measurement Tools

    Is there any testability measurement tool available for podem or D-algorithms???please can anyone tell me what are tools for testability measurement ???
  14. Closed: LabView FPGA implementations in xilinx boards

    Hello,
    Is it possible to implement LabView-FPGA designs into Xilinx boards like atlys,genesys ???
    Please can anyone tell me the suggestions?
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    [SOLVED]Closed: Re: D-Algorithm for test pattern generation

    Hello dpaul,
    Thank you very much for your valuable response......yes for generating test patterns, D-algorithm/podem algorithm steps by using verilog.
    and till now I am not used ATPG tools...I...
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    [SOLVED]Closed: D-Algorithm for test pattern generation

    Hello,
    For generate test patterns how to apply d-algorithms/podem algorithms steps using verilog??

    Please can anyone tell me the procedure how to apply d-algorithms process using verilog???
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    Closed: Re: 1 Million endurance Flash chip

    most probably it will be greater than 1 million.....
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    [SOLVED]Closed: Re: asynchronous counter for testing

    ok.now i am understand... thank you very much for ur valuable response....i have another doubt how to apply the d-algorithm based concepts for asynchronous circuits using verilog????
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    [SOLVED]Closed: Re: asynchronous counter for testing

    yes Theoretically it is possible to do...but its difficult to implement and generate test patterns..
  20. Replies
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    [SOLVED]Closed: asynchronous counter for testing

    is it possible to generate test pattern generation for asynchronous counter????
  21. [SOLVED]Closed: Re: Hangup in registration to obtain Synopsys-tetramax ATPG tool

    Thank You I will follow the process
  22. [SOLVED]Closed: Hangup in registration to obtain Synopsys-tetramax ATPG tool

    Hello,
    How to download synopsys Tetramax-ATPG tool ??? Please can anyone tell me procedure to Tetramax tool download ?
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