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  1. Closed: Re: 12v DC proximity detector for use on truck (2-3 feet range)

    That's what I gather from the OP's first post.

    Besides I work in a location with a crappy parking lot design that has a choke point in the lot that has straight in parking on both sides where if...
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    Closed: Re: readback the firmware Cyclone IV

    Like I mentioned I haven't used Quartus tools in decades, so I wasn't sure that there was a way to read a EPCS in system with the only connection to the EPCS being the FPGA. I was mistaken in...
  3. Closed: Re: 12v DC proximity detector for use on truck (2-3 feet range)

    Awsome...

    1) ultrasonic sensor
    2) Arduino + sw
    3) camera

    Sensor catches something getting close to your vehicle, Arduino SW detects this condition and triggers the camera to record, when they...
  4. Closed: Re: 12v DC proximity detector for use on truck (2-3 feet range)

    Ask google/audi/mercedes/bmw/toyota/etc for help. They've spent billions on trying to determine if an object is a ball, cat, dog, human, car, truck, etc. I might be wrong but there is probably no way...
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    Closed: Re: readback the firmware Cyclone IV

    I'm not sure you can use the Intel tools to read the entire EPCS data from device to reprogram another EPCS device or the same device. It's been a long time since I used Altera/Intel but I'm pretty...
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    Closed: Re: readback the firmware Cyclone IV

    How is reprogramming the Cyclone IV FPGA going to fix the board? The Cyclone IV is SRAM based and loses it's configuration when powered off. If the FPGA was damaged then just replace the FPGA. Unless...
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    Closed: Re: Data Transfer over long rwisted pair cable

    Metanoia? I don't think that software solutions company actually makes products.

    Do you mean Motorola, which is now part of Arris?

    You won't find much information on the inner working of any of...
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    Closed: Re: Small Project to solve Big Problem

    Seems to me it would be a lot easier (cheaper/less hassle) to just count (either in your head or out loud). And train yourself to never release until the count expires.

    I have no idea how...
  9. [SOLVED]Closed: Re: Generating Sine Wave Through External DAC (STM32)

    Either what every you do outside the for loop takes too much time or starting up a new for loop takes a lot of time.

    I'm not a SW engineer so I don't know how long it takes SW to set up a new for...
  10. [SOLVED]Closed: Re: Generating Sine Wave Through External DAC (STM32)

    The equation is the problem.
    sin( I * 6.28/360)

    Try plotting it in excel or something.

    sine has a full cycle from 0 to 2pi. You are indexing from 0-511 and end up going from 0 to 511/360*2pi...
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    Closed: Re: vhdl problem debug help please

    Untested but your code should be something like this for a counter using your 2 process FSM style.
    if (Reset = '1') then
    Count <= (others => '0');
    elsif rising_edge(clk) then -- this is the...
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    Closed: Re: Logic duplication and optimization

    This may have changed since decades ago, but I had the opportunity in a training class to run synthesis (with an identical addition structure as the OP's example) using Leanardo, XST, and Synplify....
  13. Closed: Re: How I can make use of the resources of only certain regions of the device in Viva

    You can use pblocks. As a starter you can read over this document. Search for pblock to get some information on it, then you can look for it in some of the other documentation.

    You might want to...
  14. Closed: Re: hello i when i compile in quartus i have to whait 5 hours and not done ?

    My only suggestion are the large ROM array's which are most likely not being implemented in a RAM block as ROM, that could easily explain the long compile times as a ROM implemented in logic (LUTs)...
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    Closed: Re: Timing constraints using a PLL.

    Based on your own description of what you are currently doing, you've been writing software prior to FPGAs. You are now thinking of HDLs as programming, you are writing hardware descriptions in a...
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    Closed: Re: PCB Christmas tree Ornaments

    Conflicting statements IMO.

    Batteries are not lightweight, if they are they have little to no capacity and therefore don't last long, which means you are changing batteries all the time.

    If you...
  17. Closed: Re: Loosing data in verilog in case of calculation of variance?

    I'll try again, since you seem to have ignored my previous post.

    Your data is right justified, e.g.
    datatex*sf
    datatext = 00000101_00000000
    sf = 2**-8 = 1/256 (i.e. right shift by 8)...
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    [SOLVED]Closed: Re: filtering a output of xor-ed signal

    This is what I mean


    _______ _______ _______ _______
    clk1 _| |_______| |_______| |_______|
    ___ ___ ___ ___ ___ ...
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    [SOLVED]Closed: Re: filtering a output of xor-ed signal

    They just did tell us, they are using the output as a clock. You can see it is a 90 degree phase shifted version of the yellow clock. Though they would be better off using a D-Flip-flop and a...
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    [SOLVED]Closed: Re: filtering a output of xor-ed signal

    You can't remove the glitches, that is how combinational logic works. Besides across temperature, different lots of parts, and voltage you will have different timing and a different glitch behaviour....
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    Closed: Re: Reduce Net delay in FPGA synthesis?

    it doesn't meet timing, what timing!? The path has no constraint, so it does meet timing as you've told the tool there is no timing to meet.

    Give the path a constraint then if the tools report a...
  22. Closed: Re: Loosing data in verilog in case of calculation of variance?

    Looks to me like all the data is right justified and there is nothing being done to set the fixed point to a scaling factor of either 2**-4 or 2**-8 (comment does not match parameter).

    As...
  23. Closed: Re: Error (10028): Can't resolve multiple constant drivers

    Ugh, why use two lines do the same thing that can be done in one line. I also think the one line is easier to see is a shift register (at least to my hardware centric brain).

    always @ (posedge...
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    Closed: Re: Reduce Net delay in FPGA synthesis?

    zerox100,

    I seem to remember you've been told before to constrain your design.

    Note the heading of the aforementioned net is an unconstrained setup path, with infinite slack, so yeah expect the...
  25. Closed: Re: FPGA program has some hard to trace glitches

    You are describing what is already in an asynchronous FIFO, which I think the OP has said doesn't work.

    It appears that the OP may not know how to deal with a fill/drain problem of...
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