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  1. Replies
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    Closed: Understanding of noise figure

    Hi,

    From the equation of cascade noise figure, we can see that the noise figure of the chain is determined by the first several stages of LNA. But how to physically understand it? Why is cascade...
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    Closed: Re: Dual feed patch antenna with single connector

    156105156106

    you can use delay line or hybrid. Or you can create an array.
  3. Closed: question about Friis equation with very large antenna gain

    Hi,

    in Friis equation, if the gain of transmit and receive antenna are very high, at least from this equation we may have Pr/Pt larger than 1. But since antenna is passive, it's not possible for...
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    Closed: In-band image problem for low-IF receiver

    Hi,

    For a low-IF receiver, how do we deal with the in-band image problem?

    take this figure for example, say that it's a low-IF receiver with f_IF = 1 MHz. Thus the image for one channel could...
  5. Closed: Re: How does intermodulation affect receiver system?

    Thanks!

    Can I understand it as IM product of channel 1 and 2 will rise up the noise floor of channel 0, which degrades the sensitivity at channel 0?
  6. Closed: How does intermodulation affect receiver system?

    Hi,

    In receiver design, we care very much about linearity and the IIP3 of the receiver must satisfy some requirements. But how is intermodulation affecting the receiver system?

    I saw from the...
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    Closed: Re: Why should LNA also care about IIP3?

    Thanks!

    Do you mean that the base station is transmitting signals for A, B and C simultaneously? So all these three signals will arrive at A, which means signals for B and C may be blockers for A?
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    Closed: Why should LNA also care about IIP3?

    Usually LNA works in linear region, but some text books and documents say that sometimes there can be "blocker" signals which may force the LNA into non-linear region.

    My question is what's source...
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    Closed: Re: Problem about amplifier biasing circuit

    But that's where I'm confused. If Ld doesn't need to be large, why do we sometimes need a RF choke?
  10. Replies
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    Closed: Problem about amplifier biasing circuit

    Hi,

    For CMOS integrated LNA in this picture, is LD a part of the matching network?

    Usually if LD and C1 is a bias Tee, LD should be a RF choke and C1 should be a DC blocking cap. But such...
  11. Closed: How to calculate Signal Power using ADC samples?

    Hi, I'm going to test the performance of an antenna, but unfortunately the antenna is connected to the receiver front-end and ADC on the board and cannot be separated from the board. So the only way...
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    Closed: GNURadio matched filtering

    Can GNURadio do matched filtering for code? For example the gold code for of GPS signal. Can GNURadio do binary sequence matched filtering? It seems that I can't find any demo online.
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    546

    Closed: Re: Question about transistor on MMIC

    Thanks a lot. So do you mean first simulate the layout without the transistor, and then simulate the transistor model and the layout EM model together? But how do we consider the connection of the...
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    Closed: Question about transistor on MMIC

    For example we're going to design a power amplifier in ADS, we usually do device simulation then schematic simulation and then layout and EM simulations. In the layout phase, how do people place the...
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    Closed: Re: LNA stability question

    Thanks a lot for your reply!
    1.2. I tried different simulations and found that this is the most effective way.
    3. I'm trying to make it unconditionally stable from 0 to 6 GHz, so I don't think I...
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    Closed: Re: Question about LNA stability resistor

    Thanks a lot.

    I used via ground and it still satisfied the stable condition. So is my design okay? Or should I make the stability factor larger?(like larger than 2.0?)
  17. Replies
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    Closed: LNA stability question

    151490

    151491

    Don't know what's happening to my last thread but it seems to be disappeared.

    I'm trying to design a LNA at GPS L1 band frequency. To stabilize the amplifier, I put a 20 ohm...
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    Closed: Question about LNA stability resistor

    151487

    To unconditionally stabilize the amplifier, I put a shunt resistor of 25 ohm after the transistor. Since my Vce is 3V, the resistor is going to consume about 0.2W of power. Is this resistor...
  19. Closed: Re: Question about biasing network of simple RF amplifier

    151462

    Thanks for your reply. I have another question. In this picture, I was told that the fan shape stub is a quarter wavelength open stub, which makes a short at the DC feeding point for RF...
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    Closed: Question about single balanced mixer design

    I'm trying to design a microstrip line based single balanced RF mixer using 90° hybrid and 2 schottky diodes.
    151444
    In this picture, is that matching network going to match the diodes to 50 ohms?...
  21. Closed: Question about biasing network of simple RF amplifier

    151442

    In this biasing network, what is the RF bypass capacitor for? And what is that resistor R for? My understanding is that the capacitor will prevent RF signals to go to DC source. Is it...
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    Closed: Question about GPS receiver bandwidth

    I'm trying to build a simple GPS receiver using microstrip components. If I'm correct, I think the bandwidth of GPS L1 band is about 25 MHz. I tried to build a 5-order coupled-line filter in ADS with...
  23. Closed: Question about electric and magnetic Hertizian dipoles

    If I'm correct, if I put a electric current dipole along X axis, and a magnetic current dipole along Y axis (both sources are at the origin), I think I'll have an antenna that is almost only...
  24. Closed: Re: [Verilog] Modelsim problem of enum in simulation

    Thanks! I defined STATE in a .vh file and included this file in both module an testbench, but Modelsim still created 2 unit packages. How can I fix this problem?
  25. Closed: [Verilog] Modelsim problem of enum in simulation

    For system verilog, I use "typedef enum {WAIT, WATCH, ASSERT} STATE;" in both module and testbench. The compiling is passed but when starting simulation, here comes the error:



    In both module...
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