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Type: Posts; User: Dominik Przyborowski

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  1. Closed: Re: Resistor mismatch hand calculation and simulation

    There is something called "error propagation law". This should be teacher at every school during laboratory measurement, so you should be able to find a lot of materials on it.
  2. Closed: Re: SFDR of DAC obtained from its INL and DNL

    The only thing you can get is an upper limit of SFDR, by projection of generated sinusoidal waveform through DAC transfer function. However, it can be still far away from true SFDR of your DAC
  3. Closed: Re: Transimpedance amp for DC only (bandwidth limited)

    In general input capacitance for TIA is a source of both instability and noises (in 1st approximation noise is linear with input cap).
    I would suggest to integrate signal more (by increase Cf) and...
  4. Closed: Re: Rplpoly layout matching problem

    Compare netlist. How resistors are instantiated in schematic netlist and what is added into extracted netlist.
  5. Closed: Re: Combine circuit and Verilog in Cadence

    Yes, it is. Take interest in the mixed mode simulations. You will need an ams simulator. In virtuoso IC installation directory you should have documentation for it (you can find it directly from CIV,...
  6. Closed: Re: DNL/INL Measurement in Cadence for DAC

    The links discussing measurements of D/A converter nonlinearity.
    Histogram method has nothing to do with DACs.
  7. Closed: Re: Current reference design for CS-DAC

    Ad a) start from one number, make parametric sweep to find optimum
    Ad b) don't mix saturation and inversion level. It is not the same.
    Start with W/L=1 for 1uA for nmos and 3 for pmos and look on...
  8. Closed: Re: Current reference design for CS-DAC

    ad 1) if some of transistor consumes almost all Vdd it means, there is no current in this branch and such transistor is probably cuted-off (or guy below).
    ad 2) In your 2ĩA branches you have...
  9. Closed: Re: How to change the m factor (multiplication factor) for Instances in cadence

    Really? Sorry fellow but this question asking for RTFM.

    To instantiate any device in netlist unique name is needed. So to instantiate device, for example simple resistor as vector, you need to...
  10. Closed: Re: Cadence Virtuoso - Border sheet locking / move to background

    Selection filter is your friend. Open it, switch off proper object type and voilā
  11. Closed: Re: How to change the m factor (multiplication factor) for Instances in cadence

    Your PDK doesn't support multiplier parameter. You have to instantiate as vector as erikl said.
  12. Closed: Re: 1dB compression point and jamming signals

    P1dB is commonly specified for all radio RXs and discussed in every book/article about radio RX.

    Ideal case is infinity.
  13. Closed: Re: ADE-XL: 2 tests have a same variable but it is constant for test1 and swept for t

    You already found an answer. ADE XL doesn't allows to sweep design variables, only global ones. This was changed in 6.17 by introducing ADE Assembler.
    To overcome your issue, let define a new...
  14. Closed: Re: Understanding the inversion coefficient proposed by EKV

    Ad A. It is possible and using EKV in simulation is not necessary. However, you need to characterise transistors (simple dc sweep to get gm/Id curve and extractspecific current). The most common...
  15. Closed: Re: CMRR is less than the DC differential gain

    Dc operating points for schematic and extracted views. What they are?
  16. Closed: Re: Varactor C-V Curves In Cadence

    The simplest way is to use ac analysis and measure imaginary part of current.
    For a very low values of Vds and/or Vgs negative capacitance or asymmetrical (Cgs not equal to Csg) is nothing...
  17. [SOLVED]Closed: Re: Rational Approximation of Gaussian LPF

    I have no idea what is used by ADS (i have not touched it even). As I mentioned, the only known for me case is an approximation of Hurwitz polynomials. The odd order polynomials has only complex...
  18. Closed: Re: CMRR is less than the DC differential gain

    Compare the current consumption and dc levels between schematic and extract (I suppose you are using OA views, nor spf netlist - correct me if my assumption is wrong).
    Generate device only...
  19. Closed: Re: CMRR is less than the DC differential gain

    Transient simulations giving similar results? How you generates post-layout netlist?
  20. [SOLVED]Closed: Re: measuring the parasitic capacitance at a certain node in cadence

    What would you like to do?
    1. Simulate capacitance at specific node?
    2. Extract capacitance for all nodes?
    3. Read parasitic capacitance from extracted view?
    What views you have?
    What tools...
  21. [SOLVED]Closed: Re: measuring the parasitic capacitance at a certain node in cadence

    Yes, it is.
  22. Closed: Re: Installing Cadence , Assura , EXT and MMSIM in Ubuntu

    In theory it can be installed on any Linux distribution.
    In practice, the only blessed by Cadence is RHEL 6.
    It means, on RHEL it works always, on other distros you need to know how to married them...
  23. [SOLVED]Closed: Re: Rational Approximation of Gaussian LPF

    The quassi-gaussian filter (bandpass, with quassi-gaussian impuls response) is CR-(RC) ^n, and for n>4 is no big difference.
    The mentioned by you Hurwitz approximation is the only one close to gauss...
  24. Closed: Re: Adding a pulsed switch to a dc voltage source in cadence library

    The author is so unclear...
    What I have understood, the point here is to have square wave with 50MHz frequency, and levels between ground and vdd, while vdd is defined by another vdc source. This...
  25. Closed: Re: Adding a pulsed switch to a dc voltage source in cadence library

    It seems you try to do simple thing in very complicated way.
    Describe once again what you would like to achieve. It can be graphical explanation too.
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