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Type: Posts; User: fragnen

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    Closed: Re: scan chain inside memory

    That I am aware memory bit cells are not tested through scan chain.

    What can there be inside the memory that requires scan input? Why did you talk of MBIST, JTAG and BIST?
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    Closed: Re: Gate Level Simulation

    But the equation in .lib may not be similar to the model file. For example if a D-fliplop is taken its behavioural code is understood as a D-flipflop but the equation of it does not reflect the...
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    Closed: Re: scan chain inside memory

    Aware of MBIST, BIST, JTAG. Can you please state what are those scan-in pins for in the memory that are purchased. I do not have the document to read hot those memories should be tested.
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    Closed: Re: scan chain inside memory

    Memories were purchased from third part and the documents of those memories show scan pins. What scan chains are there inside this memories?
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    Closed: Re: Gate Level Simulation

    Can a .lib files of a standard cells be used instead of a verilog models of standard cell for gate level simulation?
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    Closed: Re: Gate Level Simulation

    After rtls are synthesized using a synthesis tool like Design Compiler of Synopsys, we get a netlist. The simulation of this netlist is called gate level simulation. Is it clear now?
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    Closed: Re: Gate Level Simulation

    Are not gate level simulation always done on netlists?

    The post was raised for gate level simulation on netlists.

    Regards
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    Closed: Gate Level Simulation

    Do we use .lib for gate level simulation of netlists?
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    Closed: Re: scan chain inside memory

    The reason I started this thread is that I also though in your way. The terminology is not wrong.
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    Closed: scan chain inside memory

    How can scan chains be present inside memories? What are the functionalities of these sequential cells inside a memory so that during DFT these sequential flipflops are replaced by scan flipflops.
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    Closed: Re: For doing ECO on netlist

    It will be difficult when the number of gate counts is high for the ECO.
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    Closed: For doing ECO on netlist

    How can ECO be done on netlists without using Cadence ECO tool or any tool that needs to purchase a license? Is there any free tool? Is there any way to do it without tool?

    Regards
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    Closed: Re: LEC between two netlists

    What about some of the scan related input pins of the memories?

    Regards
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    Closed: LEC between two netlists

    What extra needs to be done in the setup of the LEC to do a LEC between a netlist as golden and its DFT inserted version as revised?
  15. Closed: Re: Test and dft logic verification in flow and the lec

    What are the other DFT related logic other than scan chain, scan_enable connection that are inserted during synthesis and not present in rtl?
  16. Closed: Re: Test and dft logic verification in flow and the lec

    Is not it better to verify the test related cones also during LEC by not deactivating the test related logic and dft related logic by providing suitable constraints?

    Regards
  17. Closed: Looking for digital engineers in Hyderabad for service company

    Anybody interested to work at Hyderabad location for a service company in any areas of Digital design may contact here.
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    Closed: LEC at top level of a SOC

    Is it necessary to blackbox all modules inside a SOC to do LEC for a SOC and do a unit level LEC for each of the modules which were blackboxed at SOC top level LEC prior to run the LEC at top level?...
  19. Closed: Re: Design to state position of first one from lsb every clock for parallel data comi

    Will not in non synthesizable due to this break inside the for loop as this break is stopping the loop to continue?



    You stated that some synthesis tools have difficulty to implement...
  20. Closed: Re: Design to state position of first one from lsb every clock for parallel data comi

    Will the rtl with for loop be synthesizable ? But for loop reduces the work. If it is a priority encoder it is a big code when the width of the input data is parametrized.

    What is the bitscan...
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    Closed: DFT pins disabled during LEC

    What are the typical dft pins that need to be disabled during LEC?

    Regards
  22. Closed: Re: Design to state position of first one from lsb every clock for parallel data comi

    No it is not. Please reply.
  23. Closed: Design to state position of first one from lsb every clock for parallel data coming

    Can you please provide a design whose output will state the location of the first '1' from the LSB for an incoming parallel bit stream every clock?
  24. Closed: Test and dft logic verification in flow and the lec

    During lec we deactivate the test related logic and dft related logic by providing suitable constraints? When in the flow are these test and dft related logics are verified for the synthesized...
  25. Closed: Reset during lec between rtl and synthesized netlist

    Do the resets need to be tied to their inactive values during LEC between rtl and synthesized netlist?

    Regards
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