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    Closed: Re: Gate Level Simulation

    in theory, yes. lib files do contain the equation of the cell. in practice, no, no simulator that I know of will take a .lib as input
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    Closed: Re: scan chain inside memory

    ... this is a completely different question from your original question. I suggest you google MBIST, BIST, JTAG, boundary scan, etc. And after that, read the documentation of the purchased memory...
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    Closed: Re: Gate Level Simulation

    at a bare minimum, a verilog file of the standard cell library is needed. this should be combined with an SDF, otherwise you get some timing model that is not realistics like a unit delay model (ie,...
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    Closed: Re: Gate Level Simulation

    Yes. You need an SDF file to be simulated with the netlist. That's all.
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    Closed: Re: scan chain inside memory

    Then you have to explain yourself because clearly we are not talking about the same thing.
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    Closed: Re: scan chain inside memory

    I think you got your terminology wrong. Memories don't have flip-flops inside. Classical SRAM memory has bit-cells.
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    Closed: Re: I2C not working properly

    From my experience, I can tell you that TSMC can give you all the files you would ever need if you show you really need them. It boils down to how good your local contact person is in solving these...
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    Closed: Re: I2C not working properly

    Yes. The absolute best accuracy you can get if from spice. You could try to extract the whole digital block and the connected IO. Depending on how big the block is, spice will choke. You might have...
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    Closed: Re: Overwrite cell delay.

    Sure, this is the way we design with MMMC. But I am under the impression that the OP is trying to hack a solution for something else...
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    Closed: Re: Overwrite cell delay.

    No, that makes no sense. What you can do is marginate the value of the first liberty file you read if you want to experiment. You can artifically make the cell faster or slower on an instance basis...
  11. Closed: Re: How to fix errors in lint summary (check_timing_intent) during synthesis in Genus

    Genus documentation covers these, look for a topic called "Checking the Constraints Using the report timing -lint Command"
  12. Closed: Re: How to fix errors in lint summary (check_timing_intent) during synthesis in Genus

    Did you at least try to understand what these are? Some of these are trivial, takes one command to fix.
  13. Closed: Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Most likely no, you won't come even close to 20uW. But there is so much I don't follow in this discussion... you should be able to use retiming without special flops and you should be able to use...
  14. Closed: Re: Trends and Relationships with Threshold Voltages and Liberty Files

    going from ulvt -> hvt, you should expect a loss in performance and a gain in leakage.
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    Closed: Re: Warnings in nano route in innovus

    1 - make sure you are using a real tech lef, not some academic hacky solution.
    2 - make sure the innovus version is recommended/certified for the PDK you are using.
  16. Closed: Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    I think he is struggling with dynamic power. Either way, a mix of LVT/RVT/HVT cells will help bring dynamic and static power down. This alone won't get you a one order of magnitude reduction in power...
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    Closed: Re: vcd file generation for netlist

    Not from the netlist itself, but from simulating the netlist. Sure, that is how you do it.
  18. Closed: Re: large slack (Reg2Reg) after placement (IC Compiler & Physical design)

    this is pretty normal, timing degrades as the analysis becomes more fine-grained. you have to now identify the source and move on. maybe you need more area, maybe better floorplan, maybe RTL changes,...
  19. Closed: Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    try playing with the root attribute lp_insert_discrete_clock_gating_logic
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    Closed: Re: Time Constraints in Placement

    For an inexperienced designer/academic exercise, I would say to load one single SDC and use it all the way. In reality, you will see projects that have different SDCs for different implementation...
  21. Closed: Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    Are you forcing genus to use ICG cells? In theory, any AND gate is enough to create the clock gating behaviour.
  22. Closed: Re: How do I reduce power at synthesis stage? I cant use UPF, Clock gating or retimin

    none of this makes sense. let's start with the basics... why can't you use clock gating?
  23. Closed: Re: [moved] Adding lockup latches manually in Cadence Encounter

    ECO flow is user-driven, but I wouldn't call it manual.
  24. [SOLVED]Closed: Re: [moved] Routing signal like clock tree in Cadence Encounter

    buffering is easy, the tools will take care of it automatically. you don't need to do anything special.
  25. Closed: Re: [moved] Adding lockup latches manually in Cadence Encounter

    Not sure there is direct support for this feature, but with the ECO flow you can insert anything anywhere.
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