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Type: Posts; User: ljp2706

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  1. Replies
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    Closed: Re: Deep nwell connection

    Deep nwell just provides a well to put p-implant. And the most important thing to consider is that the p well to dn well never forward biases. That is usually done by reverse biasing to the highest...
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    Closed: Re: Deep nwell connection

    I agree. Unless you have hundreds of wells, you’re not going to save a lot of space by combining just three. There’s less risk with keeping them separate.
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    Closed: Re: MOSFET Speed and power tradeoff

    Just to clarify something, strong inversion is not the same as saturation. Strong inversion is the point where you have significantly overcome the surface potential and have created an inversion...
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    Closed: Re: DRC and LVS in Calibre

    Are you having difficulty understanding the actual violation, or using the tool? If you’re having a hard time understanding the violations, the PDK documentation usually includes a DRC manual that...
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    Closed: Re: Deep nwell connection

    Provided that you reverse bias the deep nwell to the highest of the three supplies, you can share the deep nwell. Just make sure you follow any violations/considerations implemented by the DRC rule...
  6. Closed: Re: Why we should choose even number of finger

    I think it’s primarily done for layout matching. As long as your schematic is readable, doesn’t violate pdk requirements, meets specifications, and matches your layout, it doesn’t matter too much...
  7. Closed: Re: "calibre view generation encountered a fatal error" but spectre PEX extraction wo

    What are the simulation errors? Also, what does the CIW say after the file is generated?
  8. Closed: Re: Why we should choose even number of finger

    Even numbers of fingers are better because it makes the device layout symmetric. You have two sources and one shared diffusion. In the case of a source coupled differential pair, since the sources...
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    [SOLVED]Closed: Re: Use of hybrid layer in devices

    It sounds like the layer blocks SOI from being underneath the device. They must somehow prevent surface oxidation of the wafer so the device enclosed by this shape sits directly in the bulk (the...
  10. Closed: Re: "calibre view generation encountered a fatal error" but spectre PEX extraction wo

    Not sure, I agree with one of the previous comments that you might need to check your permissions. See if you have write access to the directory that everything is stored in. That might very well be...
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    Closed: Re: tsmc13rf pdk file in cadence virtuoso

    nmos1v
    This is the 1V device (gate/drain breakdown).

    nmos2v
    This is the 2V device (drain breakdown, need to verify if gate breakdown is 2V, sometimes it is not)

    nmos3v
    This is...
  12. Closed: Re: "calibre view generation encountered a fatal error" but spectre PEX extraction wo

    After the PEX run completes, are there any other error messages in the CIW?

    Are you sure that the ground node name that you entered is correct, and is present on your layout? Try running it once...
  13. Closed: Re: "calibre view generation encountered a fatal error" but spectre PEX extraction wo

    What do your pins look like? Do you have a metal on the appropriate layer, label included too? No “illegal” names such as “+”, “-“, etc. pins should be on the “pin” layer if that’s in the pdk...
  14. Closed: Re: "calibre view generation encountered a fatal error" but spectre PEX extraction wo

    Can you provide some screenshots or details of your runset for PEX? That would make it a lot easier to debug. Also, can you list the step by step procedure of the PEX run you’re doing?
  15. Closed: Re: "calibre view generation encountered a fatal error" but spectre PEX extraction wo

    Have you tried re-running PEX after the first failed attempt? Particular versions of this tool seem to have a bug where you have to run it twice, the second time usually passes. This error reminds...
  16. Closed: Re: PMOS WELL of same bulk potential of different transistor groups

    If you put devices in the same well that share a common potential, it’ll reduce layout area. Otherwise you’ll have to ensure you have adequate spacing between the wells to pass DRC. This is...
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    Closed: Re: Port size in layout design

    It’s about location. As long as it’s covered entirely by the layer it’s on and your label is within the pin, the dimensions don’t matter
  18. Closed: Re: guard ring contacts for the PMOS transistors

    I try to fully enclose the tap on the nwell to further reduce the risk of matchup. But if you’re not seeing violations, you might be okay for now. Once you connect to io at top level, you might get...
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    Closed: Re: Layout Abutment Sitting in the TSMC PDK

    I think you can leave both contacts on. Just overlap the shape exactly and it’ll only recognize it as a single contact/diffusion. Should pass DRC that way. If not, once you overlap it, remove the...
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    Closed: Re: Layout Abutment Sitting in the TSMC PDK

    The best thing to do would be to turn off auto abutment. I never have that enabled because it’s very common to run into issues with it in layout xl. In layout xl go to: options—>layout...
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    Closed: Re: Plotting waveform in Mathlab from Cadence

    Like circuitking said, csv formats work well. if you plot the data in virtuoso, or select it in the ADEXL window, you can export as csv. Importing the data into matlab will create a vector that you...
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    Closed: Re: current mirror matching issue

    That should be fine but you’ll want to keep them close together. The important part is that M1 matches well to M2 and that M3 matches well to M4 and MB. You won’t really be able to place them in the...
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    Closed: Re: Pin definition in TSMC 0.18um

    Sounds like it’s not recognizing the pin as a valid pin. Does the metal pin work when you via up to it? If the pin is on poly | pin and the label is on poly| label, I’m not sure what else could be...
  24. Closed: Re: devideing large MOSFET gate using muti fingers

    That depends on what process node you’re working in. What is the minimum feature size in the process you’re working in? Also, your pdk will have a section on matching. That should provide additional...
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    Closed: Re: Bulk capacitor series with 1 ohm resistor

    This capacitor+resistor in parallel with another capacitor configuration is used to dampen inductive resonance in power supplies due to the interaction of parasitic inductances with bypass...
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