Type: Posts; User: ThisIsNotSam

Page 1 of 20 1 2 3 4

Search: Search took 0.05 seconds.

  1. Closed: Re: [ Describing PG Pins at RTL Level UPF ]

    This is so confusing. What tool are you using, to begin with? What step of the flow are you doing? I can't think of any tool that takes RTL and UPF files.
  2. Replies

    Closed: Re: Innovus CTS .tcl Script Qustions

    I believe the tool is now able to find all clock roots automatically. Maybe they are inferred from the SDC commands.
  3. Replies

    Closed: Re: Innovus Command Questions

    Cadence has a really terrible time keeping the documentation synced with the new versions. Just stop using these commands and look for the new equivalent ones.
  4. [SOLVED]Closed: Re: Short violations in Innovus (due to special route)

    Check the well connections for these cells. Make sure the pins are named the same way as in the std cells. Just a hunch.
  5. [SOLVED]Closed: Re: Short violations in Innovus (due to special route)

    - check global net connections twice, and then check again. I don't understand your description of this internal power net and why that would be a problem.
    - run real DRC, don't trust Innovus DRC.
  6. Replies

    Closed: Re: Realistic Monte Carlo setup

    I could see Case 2 generating a wider distribution than Case 1, i.e., more pessimistic. My understanding is that this is exactly what foundries are trying to avoid when they recommend Case 1. I would...
  7. Replies

    Closed: Re: Realistic Monte Carlo setup

    Well, yes and no. Foundries recommend a mix of global and local MC, just like the OP mentioned. In my experience, case 1 is the prefered method these days. Based on the terminology I am almost...
  8. Closed: Re: Does Opentimer tool for STA support VHDL netlist

    even if it doesn't, converting a netlist from vhdl to verilog is rather trivial. Both DC and genus can do it for you.
  9. Closed: Re: DIE Size calculations in TSMC22ULL GF""FDX

    Not sure we can share previse numbers without giving away specifics of the technology. You can typically find some *rough* numbers in the marketing material/press release when the nodes mature into...
  10. Closed: Re: CPU, DRAM, VNAND - why can't they be integrated together on a single SoC?

    dick's answer is really thorough. it's all about the trade-off of market needs vs cost. we are not in a situation where most customers would benefit from embedded DRAM or NVM, so you got to pay a lot...
  11. Closed: Re: CDC RTL Simulation vs non-CDC RTL Simulation

    it's not about the simulator support, it's about how the gate is described in verilog. check the .v file that came with your std cell library, it might account for metastability in very funky ways or...
  12. Closed: Re: Are parallel universes source of high fault coverage of sequential ATPG

    no. .
  13. [SOLVED]Closed: Re: Derate Factor while calculating delay

    derate factor is helpful for some simple rule of thumb estimation here and there. say, you are porting your design to a new library that is promised to be 10% faster. you can use the old library,...
  14. Replies

    Closed: Re: Verilog modulus % operator

    I think you won't find that precise of a statement in any of the vendors' documents since they have synthetic/designware libraries that support a lot of arithmetic functions, including modulus. See...
  15. Replies

    Closed: Re: Regarding synthesis of HDLs

    learn what the inputs are: RTL description, library, constraints
    learn what the outputs are: mapped netlist
    learn the tricks in the middle: clock gating, retiming, scan insertion, power analysis,...
  16. Replies

    Closed: Re: Innovus CTS .tcl Script Qustions

    We are going in circles now.

    Not only you do not need a ctstch file anymore, my understanding is that you should not use one. There should still be a legacy mode within the ccopt_design command to...
  17. Closed: Re: .sdc file into Innovus WARN and ERROR

    I think so. Stick to the MMMC model. You can debug it visually using the MMMC browser. Should be very easy to spot is something is wrong.
  18. Closed: Re: .sdc file into Innovus WARN and ERROR

    SOCE = soc encounter, yes

    if your errors are only related to wire load models, just remove those lines. they are important for logic synthesis, not for physical synthesis. if you need to specify...
  19. Replies

    Closed: Re: Innovus CTS .tcl Script Qustions

    1. first part of the question, regarding route guides, I can tell you what they are. these are high level "regions" that help the router estimate resources available. not sure what CTS does with this...
  20. Closed: Re: Synopsys cell Library "lec25dscc25_TT" required.

    unless the library is academic, no one can provide the files to you. NDA infringement.
  21. Closed: Re: Including geometric variation of transistors using Montecarlo simulation in Cade

    Do you have any model you can play with? The answer to this question becomes quite trivial when you see how foundries organize their models, corners, and process variation distinction (global and...
  22. Replies

    Closed: Re: Boundary Cell in Core Chip

    I don't know what you mean when you say boundary cell. endcap is clear, that is industry lingo. this is how you terminate std cell regions.

    The term PR boundary is used, but there is no cell that...
  23. Closed: Re: Sequential ATPG errors that dont go away because of hardware metal faults

    I would suggest to stop drinking.
  24. Replies

    Closed: Re: Timing ARC for Asynchronous Signal

    the rule is simple: any input that causes a change to an output is considered during std cell characterization. the tools that are farther up in the implementation chain need to know the delay and...
  25. Closed: Re: Getting connectivity information from fsdb file

    VCD file is not meant to store netlist/connectivity. You can simulate a VCD along with a netlist, if that is what you are asking...
Results 1 to 25 of 500
Page 1 of 20 1 2 3 4