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  1. Closed: Re: Excessive space needed for Transient analysis Cadence

    Sorry. Attached you can find the netlist, including the name of the simulator, spectre. https://drive.google.com/file/d/1dfh3qWjHLPSE2WPHE6YinBT8Utf-HCE-/view?usp=sharing
  2. Closed: Re: Excessive space needed for Transient analysis Cadence

    Hi, Attached you can find the netlist, which is a ring oscilator. The option settings for the transient analysis in ADEL Cadence. And the data generated when downloaded in .CSV file. Is important to...
  3. Closed: Excessive space needed for Transient analysis Cadence

    Hi, I have run transient analysis in ADEL and the data points taken for the signal are too many, 500 kB of data generated for 3us of transient analysis. How to reduce this points taken by ADEL?...
  4. Closed: Re: Remove glitches in output frequency of ring oscillator

    Thanks for your comments. Look I am testing a library, so is not really about a target frequency, instead is about a proper test on the inverters that I have in the library and specially using RO. Do...
  5. Closed: Re: Remove glitches in output frequency of ring oscillator

    @dick_freebird, thanks for your reply. The signal as it shown in the screen shot remains the same, no sub-cycles. But is different for each aging time. What could be a better initialization or logic?...
  6. Closed: Remove glitches in output frequency of ring oscillator

    I am making tests with a ring oscillator (RO) in ADEL Cadence. But when I increase the size of the RO from 13 to 121 stages there are glitches in the output signal of the RO (image attached). How can...
  7. Closed: How does aging is conducted exactly in Cadence?

    Hi
    I am runing aging simulations using ADE XL and I would like you to confirm my theory. Does the aging is conducted by measuring the signal in the transient time analysis specified? Why does the...
  8. Closed: Re: CMOS ring oscillator frequency degradation through years

    Hi ThisIsNotSam
    I am using the same Unified Reliability Interface (URI) file in both tools. And also the same model. The only thing that is changing in ADEXL is an advanced additional arguments ...
  9. Closed: CMOS ring oscillator frequency degradation through years

    Hi
    I am ruining simulation in VIrtuoso-Cadence, with 13 stage RO (22nm technology) and I am getting a weird frequency degradations. In the 1st case, I am runing the simulation using the tool ADE-L...
  10. Closed: Calculate the load capacitance in oscillators

    Hi
    I am using a ring oscillator like the one attached and I am wondering how to calculate the CLoad in this case. Because I want to do some tests in stressing the circuit but I am not sure what...
  11. Closed: Re: Add output signal to reliability analysis virtuoso-cadence

    Hi
    I am using ADE. I've have tried to add I(Vdd) but it doesn't show up in the list of signals. Specifically I would like to add: Ileak, Idrain and Vth during the aging time of 5 years. 153464
  12. Closed: Add output signal to reliability analysis virtuoso-cadence

    Hi all

    How to add the leakage current, drain current and Vth in a reliability analysis in Virtuoso-Cadence? So far the only output provided by the simulation is the frequency. The circuit that I...
  13. Closed: [moved] Saving data from reliability simulation Virtuoso Cadence

    Hi all

    I am running reliability simulation using Virtuoso Cadence. I would to save the full aging data of 10 years. How can I do this? I also want to save current and frequency of the ring...
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    Closed: Re: Compatibility question Cadence

    Dominik Przyborowski

    [SOLVED]Installing xfonts-base and xfonts-100dpi packages SOLVED IT. Thank you.
  15. Replies
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    3,976

    Closed: Re: Compatibility question Cadence

    Hi Dominik Przyborowski

    Thanks for the reply. I am using RHEL. The log file lxa:87.log looks like this:
    152164
  16. Replies
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    3,976

    Closed: Re: Compatibility question Cadence

    Hi Dominik Przyborowski

    In the simulator mode I am choosing Spectre native not RelXpert.
    1. Do I still need RelXpert?
    2. What is the command in the linux terminal to check the RelXpert...
  17. Replies
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    Closed: Re: Compatibility question Cadence

    Hi Dominik Przyborowski
    1. I can run other analysis, like transient. But this reliability is just not running.
    2. The virtuoso is checked out successfully. No problem with that.
    3. The last...
  18. Replies
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    3,976

    Closed: Re: Compatibility question Cadence

    I have encountered an issue related with a file that cannot be reached. The message window says that "ICRP is not found in the remote machine", following you can find a screenshot: 152122
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    Closed: Re: Compatibility question Cadence

    Hi BigBoss
    Thank you for your reply. What is happening is that am using is Virtuoso ADE Assembler, but the reliability simulation is failing. I am ruining this following the reliability_lab from...
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    Closed: Compatibility question Cadence

    Dear all

    Currently, I am having issues completing the reliability analysis in Virtuoso ADE Assembler. And I was checking the versions. Is there any compatibility issues between the following...
  21. Closed: Troubleshooting Virtuoso ADE assembler

    Dear all

    Currently I am running the reliability analysis using Virtuoso ADE assembler. But I have encountered an issue related with a file that cannot be reached. Does anyone know how to trouble...
  22. Closed: [moved] The Virtuoso Unified Reliability Interface (URI)

    Dear all

    I am looking for an example of a Unified Reliability Interface (URI) set up and mainly a file example. This is used in Virtuoso Cadence to add your own aging models to the Virtuoso MMSIM...
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    Closed: Cadence aging model for aging simulation

    Dear all

    I am looking to perform aging simulations using cadence. Recently I read that "Some foundries use the Spectre® AgeMOS built-in model for Aging, while others use their proprietary model...
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    Closed: Re: push button to select a number verilog

    Hi KlausST, thank you for replying

    I want edge detect, because I want to select a number just in each edge.
    About the clock, yes, is actually 50MHz, and what I want is to select only when I...
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    Closed: push button to select a number verilog

    Hello, I need some help on pressing a button to select a number, but only when I press the button (negedge), the button can be pressed long time with no more changes on the number selected. So far...
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