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Type: Posts; User: ibtesam90

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  1. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Thanks to all who guided me. I am able to resolve the issue and get the right simulation results. The workaround, which resolved the issue for me, is to manually define the VSS and VDD terminal in...
  2. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    I checked *|Net section and i found the following code:
    "

    *|NET VIN 0.000819726PF
    *|I (MM0:GATE MM0 GATE I 5e-17 -3.79 4.29) // $llx=-3.79 $lly=4.29 $urx=-3.79 $ury=4.29 $lvl=30
    *|I (MM1:GATE...
  3. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    Here is the result of that SPF file. It contains the VDD and VSS.

    "*
    *|DSPF 1.3
    *|DESIGN inverter
    *|DATE "Tue Oct 22 23:50:15 2019"
    *|VENDOR "Synopsys"
    *|PROGRAM "StarRC"
    *|VERSION...
  4. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    I am a novice in this. by the extraction script you are referring to .tcl file and then running it on console. I am using GUI following the guide from following link:...
  5. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    I am using Synopsys Custom Designer. I tried to search the using "DSPF" in my working directory. only files that comes up with this search are the OA2DSFP.tech files in Lstarrc.lpe folders and they...
  6. Closed: Re: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    yes, I did put text labels using "M1PIN". All the four labels i.e., VDD, VSS, INV_IN and INV_OUT. The Layout VS schematics is passed without any errors.
  7. Closed: Synopsys Custom Designer; simulation error for LPE in Inverter cmos circuit

    I am designing a very basic gate (inverter) in custom designer using SAED PDK90nm. I am able to create the schematics and layouts and generate Parasitics. When I run the simulation on testbench...
  8. Closed: Re: Can't Read SAED32nm libraries for design compiler

    Thanks for the suggestion. It worked but even after reading the libraries Compiler is unable to link the design.
    I am using a benchmark circuit s298 form ISCAS89 benchmark circuit. The following...
  9. Closed: Re: Can't Read SAED32nm libraries for design compiler

    154560
    I have attached the screenshot after the said changes. I hope I got what you wanted to say.

    Still getting the same error.

    Pardon my ignorance, I am new to this thing.
  10. Closed: Can't Read SAED32nm libraries for design compiler

    Hello everyone!
    I am new to Synopsys tools and i am having trouble using the 32nm libraries provided by Synopsys.

    I am trying to set the link libraries through following command:
    set...
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