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  1. Closed: Re: Can IP(Intellectual Property) open source, what does good business model?

    open hardware and open EDA initiatives exist for decades now... but I am not aware of any success story worth mentioning. VHDL is a good one, but it is not IP per se. opencores is a nice repository,...
  2. Closed: Re: How to choose a good university for electronics engineering in USA?

    don't forget tuition. you might be looking at 200k debt after two years of study in the US.
  3. Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    Agreed. The effects are wild, the layout is not. That was my point.
  4. Closed: Re: CMOS FINFET Layout Tutorials/Explanations

    there is nothing special about a FinFET transistor. You have less flexibility than in older technologies. You will never draw a fin, for instance. It is always there, it is gridded and always...
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    Closed: Re: will get antena effect in poly

    Technically, you could. If the process utilizes CMP, of course. But how likely are you to use poly to route long distances? I am sure you will bump into DRC violations before you bump into antenna...
  6. Closed: Re: Finding certain string in file using bash shell scriot

    Literally every programming language or scripting language can be used for parsing this. Use whatever you are more comfortable with. sed/awk look like good candidates here.
  7. Closed: Re: What cells are placed around RAM? Why?

    not sure what you are asking. right beside the SRAM macro you don't place anything, it's empty space left that way on purpose for routing signals in/out and for power isolation.
    on the macro itself,...
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    Closed: Re: default statement in case

    I have seen people have different opinion on this matter. Some say it increases readability. Some say they HAVE to use because of internal company coding styles.
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    Closed: Re: Site row overlapping

    https://images-na.ssl-images-amazon.com/images/I/41skqXGd1GL._SX425_.jpg
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    Closed: Re: Site row overlapping

    then fix the floorplan. you are creating standard cell areas on top of already existing std cell areas. this is what site overlap means.
  11. Closed: Re: How to identify design in terms of track ?

    number of tracks is a property of the standard cell library. it effectively means the height of the cells. it is weird to refer to a design as being X track design. a design can have many blocks, and...
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    Closed: Re: Site row overlapping

    context? are you talking about floorplanning?
  13. [SOLVED]Closed: Re: Post place & route netlist simulation is failing although STA is ok

    Happy ending :)
  14. Closed: Re: How to declare a variable number of parameters

    Did you try compiler directives? You can get it done with
    `define but it might look ugly.
  15. Closed: Re: For DFT perspective ,what happens when there are no capture clock

    Is your design academic in nature? Most designs don't have this characteristic, outputs are flopped and for very good reasons.
  16. [SOLVED]Closed: Re: Post place & route netlist simulation is failing although STA is ok

    Hmm. You need to debug gate by gate, see how much delay the simulation is showing vs how much STA is showing. It has to match very well.
  17. [SOLVED]Closed: Re: Post place & route netlist simulation is failing although STA is ok

    This type of thread pops up here very regularly. You seem to be wiser than the typical poster, but maybe we should review the basics. The number one reason why gate level simulation fails is the...
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    Closed: Re: scan chain inside memory

    You are going in circles now. You started this thread saying exactly the opposite.
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    Closed: Re: Gate Level Simulation

    what do you want me to say? if you try to hack a solution, you get as far as the hack takes you. there are standard ways of doing things, stick to those and you will not have to worry about model...
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    Closed: Re: scan chain inside memory

    I can only make an educated guess that the memory also has some controller logic or buffer that is implemented with flip-flops and that those are tested through a conventional scan chain. The memory...
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    Closed: Re: Gate Level Simulation

    in theory, yes. lib files do contain the equation of the cell. in practice, no, no simulator that I know of will take a .lib as input
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    Closed: Re: scan chain inside memory

    ... this is a completely different question from your original question. I suggest you google MBIST, BIST, JTAG, boundary scan, etc. And after that, read the documentation of the purchased memory...
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    Closed: Re: Gate Level Simulation

    at a bare minimum, a verilog file of the standard cell library is needed. this should be combined with an SDF, otherwise you get some timing model that is not realistics like a unit delay model (ie,...
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    Closed: Re: Gate Level Simulation

    Yes. You need an SDF file to be simulated with the netlist. That's all.
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    Closed: Re: scan chain inside memory

    Then you have to explain yourself because clearly we are not talking about the same thing.
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