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  1. Closed: Re: Changing the ModelSim version that comes with Libero SoC v12.3

    Well I did ask for that and the local FAE told me that it won't be provided.
    They will provide the compiled libraries for the 64bit DE version.

    with this info I think it is appropriate to close...
  2. [SOLVED]Closed: Re: Values of set/ reset when Instantiating ODDR?

    You set the "SRTYPE" to either "SYNC" or "ASYNC" depending on the reset signal used in your design.
    E.g. - If you have a sync reset, then the ODDR inst will look something like this(VHDL):



    ...
  3. [SOLVED]Closed: Re: Values of set/ reset when Instantiating ODDR?

    Take a look at the ODDR for 7 series library guide.
    https://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug953-vivado-7series-libraries.pdf

    Pg 292 - 294 has port description table...
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    Closed: Re: ISCAS 89-s38417 testbench required

    I see the 'bench' files here http://www.pld.ttu.ee/~maksim/benchmarks/iscas89/bench/ also the core number you have listed.

    Was a simple google search. Is this what you are looking for?
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    Closed: Re: how to generate 4MHz clock from 2 MHz clock.

    The OP has posted the same Q in Xilinx forums yesterday and did not provide sufficient details in order to answer his Q.
    My answer to him would be the same here as there.

    The PLL/MMCM inside the...
  6. Closed: Re: How to create an IP core based on a project in ISE?

    Some help here:

    https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_coregen_ip.htm

    https://forums.xilinx.com/t5/Synthesis/Making-and-using-own-IP-on-ISE/td-p/731456
  7. Closed: Re: Changing the ModelSim version that comes with Libero SoC v12.3

    Two tickets have been logged at Microsemi last week:
    1. Provide pre-compiled libraries for DE-64 ver.
    2. They have also acknowledged the ModelSim ME 2019.2 memory leak issue.
  8. Closed: Re: Changing the ModelSim version that comes with Libero SoC v12.3

    I am sure the tool generated DO file is taking care about them. It is attached.
    If you look at line num 12, it indicates the mapped polarfire library path, which I have created and compiled for...
  9. Closed: Re: Changing the ModelSim version that comes with Libero SoC v12.3

    Update...

    Should be "the steps required to compile the libraries in order to run a non-bundled ModelSim version."
  10. Closed: Re: Changing the ModelSim version that comes with Libero SoC v12.3

    Yes, I did use the -L with the libraries.
    Following are the last lines from my DO file.


    vsim -L PolarFire -L presynth -L COREAXI4DMACONTROLLER_LIB -L COREAHBLITE_LIB -L COREAHBTOAPB3_LIB -L...
  11. Closed: Re: Changing the ModelSim version that comes with Libero SoC v12.3

    Today Microsemi has acknowledged that Modelsim ME 2019.2 that comes with Libero SoC 12.3 has memory leak problems. It will be fixed in the next version of Libero. So I will wait for this for...
  12. Closed: Re: Changing the ModelSim version that comes with Libero SoC v12.3

    It is leaking with my testbench. First I thought there might be a problem with mine.
    Then I downloaded a Microsemi Demo Project (PCIe with DMA) from their website and there also I could see the...
  13. Closed: Changing the ModelSim version that comes with Libero SoC v12.3

    I am using Microsemi Libero SoC 12.3 tool suite. With it comes ModelSim ME Pro 2019.2.
    But I cannot run overnight simulations with this ModelSim ver as it loses memory @0.1MB/sec. It is the 32bit...
  14. Closed: Re: Interface Logic Model in Synosys is obsolete

    What does the command reference manual say? Have you looked there?
  15. Closed: Re: Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA

    I know that and assumed the OP knows the difference.
    If he is a beginner in this area, it makes more sense for him to 1st understand how Ethernet frames are rx and tx before moving on to complex...
  16. Closed: Re: Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA

    You need the understand the concepts an design your own. :-)
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    Closed: Re: Modelsim Microsemi Pro 2019.2

    In my code I have a part where I am asserting a message at the Transcript window every 20us.
    Have added the flush() there. Works for me!
  18. Closed: Re: Get some advice and tips to design ETHERNET switch or even TSN switch on FPGA

    If you are using a Xilinx FPGA, I can advice you to use the TEMAC IP core (free hardware eval license) for initial understanding.
    Download and skim through its docu. Chap3 and 5 should be initially...
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    Closed: Re: Modelsim Microsemi Pro 2019.2

    Looking at the *_simulation.log I found the following...

    # ** Fatal: (vsim-4) ****** Memory allocation failure. *****
    # Attempting to allocate 131072 bytes
    # Please check your system for...
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    Closed: VHDL write to file with Modelsim Microsemi Pro 2019.2

    I am using the Modelsim Microsemi Pro 2019.2.
    In the testbench I am opening a file in write mode and periodically writing data to it. I open the file in write mode and never close the file (always...
  21. Closed: Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    An advice....
    You can assemble your experience and later create a "Blog Entry" in this forum.
    Better than updating a thread....

    Creating separate threads puts more focus to the actual...
  22. Closed: Re: FPGA Re-Verification after minimal initial verification with Microsemi IGLOO2

    Are you talking about LEC?

    Here is a list of widely used LEC tools - https://en.wikipedia.org/wiki/Formal_equivalence_checking and they are expensive.

    I have never compared netlists. Two...
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    Closed: Re: P1500 Wrapper implementation

    I can speak about the FPGA tools, specifically Vivado. They don't have capabilities of an automatic wrapper creation. You must write the RTL for it.
  24. Closed: Re: Does Opentimer tool for STA support VHDL netlist

    Did you read the paper for this tool?

    In the abstract it clearly mentions - "OpenTimer works on industry
    formats (e.g., .v, .spef, .lib, .sdc) and is designed to be parallel and
    portable. " I...
  25. Closed: Re: AVR Soft-Core (ATMega103) - issues during synthesis and implementation

    That's the only work around if you don't have a clock capable pin. If you have one try moving the signal to it.

    Having set it to FALSE, did your design pass timing? Because that is the penalty...
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