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  1. Replies
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    Closed: ABB RTU Internal Protocol

    Hello,
    Does anybody know about the internal protocol of ABB RTU560? In one of its documents, it says the internal communication of the RTU is based on IEC-101. But, when I get some data from the...
  2. Closed: [moved] 74HC4060 Oscillator/Counter Frequeny Problem

    Hello,
    I have an oscillator/counter (74HC4060) which is part of a 100%-properly-working board. The oscillator with the external resistors and capacitors, generates a 73.5 kHz pulse (pin # 9, which...
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    Closed: Re: Using CapTab for capacitance calculation

    Thanks for the information,

    I'm using this but I'm not able to translate the table, like for example for one transistor there are 7 nodes! And those are like this:
    T1:int_SI
    T1:int_GP
    T1:int_DI...
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    Closed: Error running post layout simulation

    Hi,

    I'm running post layout simulation with cadence and I'm getting this error:
    ERROR (SFE-23): "input.scs" 63: re1 is an instance of an unidentified model M2.

    I tried in two ways: First, I...
  5. Closed: The relation between an ADC's Sample-rate, Bandwidth and it's S/H Speed

    When they say, for example, a 125 MSps ADC with 2.2 GHz analog bandwidth:
    1- This is called undersampling (or sometimes IF sampling), right?
    2- What should the speed (the maximum clock frequency)...
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    Closed: Designing an Opamp with 4 GHz BW

    I'm designing an opamp and need 78 dB gain and 4 GHz BW with 3.5 pF Cload and 2.5 V supply voltage. I can get the gain with a single stage folded-cascode opamp, but the best result for the BW is just...
  7. Closed: Noise in Time Interleaved and Double Sampling Circuits

    Suppose we have a time interleaved system (e.g. ADC) with two channels, which means the input samples are used by each channel every other one. What would the total noise of the system be? Is it...
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    Closed: A Question About Delta Sigma Modulators

    I'm designing a 2nd order delta sigma ADC. I want to compare the systematic results with circuit design. In Matlab I have a 73 dB SNDR but in HSpice (all blocks are ideal) I have 66 dB SNDR. I don't...
  9. Closed: resolution of a comparator

    What is the difference between the offset and the resolution in a comparator?
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    1,165

    Closed: Re: A Question About Delta Sigma Modulators

    The OTA works in all corners well enough.
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    Closed: Re: A Question About Delta Sigma Modulators

    Of course not. The nominal voltage in 0.18 um is 1.8 V. In fact, my design is considered a low voltage design.
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    Closed: Re: A Question About Delta Sigma Modulators

    Hi,
    Thanks for your reply.
    The details are so:
    SC architecture, 1 bit quantizer, No parasitics are considered, process is 0.18 um and the supply voltage is 0.9 V.
    Thanks for your suggestions.
  13. Closed: A question about interface between Xilinx and Hspice

    I want to use my circuit (a digital circuit) which is designed in xilinx software, in hspice. In fact I want to simulate a mixed signal system. How should I do that? Can Xilinx give me a netlist?...
  14. Closed: Re: a question about hspice

    Hi,
    Thanks for your reply. That's right. It works!
    Thanks.
  15. Closed: a question about hspice

    I want to plot the drain current of a mosfet (m1) which is in a subcircuit. I use this:
    .print tran i(xopamp1.m1)
    in which xopamp1 is the subcircuit. The current is printed in the listing file but...
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    Closed: A Question About Delta Sigma Modulators

    I have designed a 2nd order delta sigma modulator. In TT 25 corner the SNR is 63.8 dB. The worst result is obtained in the SF 85 which has 33 dB SNR. I want to improve the modulator performance so...
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    Closed: how to measure output swing

    Hi,
    Thanks for your reply. Could you please send the link to download the ebook?
  18. Replies
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    Closed: opamp output swing

    When measuring the output voltage swing of an opamp, we should use a closed loop configuration. Measuring the opamp swing in open loop configuration does not make sense.
    Is that right?
    What is the...
  19. Closed: Re: A problem in Hspice regarding pole zero analysis

    Hi,
    I use Hspice 2007.
  20. Closed: Re: A question about using models for transistors in Hspice

    Hi,
    Thanks for your reply. I got it. But what is the other way foundries provide the model?
  21. Closed: A question about using models for transistors in Hspice

    Hi,
    When simulating a circuit that has several transistors in Hspice, we do not determine the model (one of the models that is defined in the library, for example nch.1 to nch.12) used for each of...
  22. Closed: Testing the frequency resonse of a CMFB circuit

    How can you test the frequency response of a CMFB circuit whose input and output are the same like this circuit which appears in [Castello JSSC 1985]?

    http://images.elektroda.net/15_1225886895.jpg
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    Closed: Re: Need help on switched CMFB

    Hi,
    The paper is attached. Hope it helps you!
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    Closed: Re: A question about bandwidth of opamp

    Hi,
    Thanks for your reply.
    I do mean GBWP, which is the unity gain frequency of the amplifier. But the GBWP can be defined so:
    ωu = Av × ω3dB
    in which Av is the amplifier gain and ω3dB is the...
  25. Closed: Re: A problem in Hspice regarding pole zero analysis

    Hi,
    Thanks for your reply.
    No, the CMBF circuit is all real.
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