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Type: Posts; User: TrickyDicky

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    Closed: Re: Advanced VHDL book recommendation

    Well that makes more sense. Ive always understood that old synthesisors (in the 90s) couldnt deal with combinatorial and sync logic in the same process, hence the need for two processes for...
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    Closed: Re: Advanced VHDL book recommendation

    I get to page three, and see this:



    use ieee.std_logic_arith.all;


    Then section 5.7 and see this:
  3. Closed: Re: looking for Advanced altium tutorial,especially with scrip and fpga

    https://lmgtfy.com/?q=altium%20tutorial&s=g
  4. Closed: Re: VHDL use of 'Z' std logic for bus, or should one use interconnect?

    Use a mux.
  5. Closed: Re: VHDL use of 'Z' std logic for bus, or should one use interconnect?

    Internal tri-states haven't existed inside FPGAs (other than the IO pins) for about 20 years. Any tri-state style code will be converted to muxes in synth tools so it should all still work.

    BUT
    ...
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    Closed: Re: Advanced VHDL book recommendation

    For a start, get a good reference guide. The Doulos ones are the ones Ive always used:
    https://shop.doulos.com/content/products/golden_reference_guides.php#Anchor-Th-61209

    As for text books, Ive...
  7. Closed: Re: Attempting to get a license for feature 'Synthesis' and/or device 'xcvu440'

    Without posting the actual errors there is little we can do to help.
    Do you have a full paid licence for vivado or are you just using the web-pack?
  8. [SOLVED]Closed: Re: Request for clarification: multiplication and hardware multipliers blocks

    Usually, it will infer a DSP block, with surrounding pipeline registers also sucked into the DSP block (or at least it should). It should also be able to infer the carry chain as needed.
    If DSP run...
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    Closed: Re: Asynchronous reset mechanism

    In your new example, enable and reset have no connection to each other.
    In your example, if reset is high on a clock edge OR the rising edge of a reset, Q is set to 0.
    I also dont understand why...
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    Closed: Re: Asynchronous reset mechanism

    Because it's a delta race - reset_sync is dropping before the clock.
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    Closed: Re: Asynchronous reset mechanism

    If it was a dynamic testbench, Id say you have a delta race. Ie. reset_wsync is dropping just before the clock edge, hence it thinks a write has occured (because reset_wsync has actually dropped...
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    Closed: Re: Asynchronous reset mechanism

    Im guessing that reset_wsync is a synchronised version of the asynchronous reset (given its name - synchronised to the write clock). Im guessing that the comments refer to the behaviour of the inputs.
  13. Closed: Re: vcom-1263 Error with generate and component instantiation

    I dont know the answer to this specifically, because I never use configurations (and Ive never seen them used or needed them).
    Unless you have multiple architectures, they're pretty useless. Even if...
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    Closed: Re: OpenCL vs VHDL running in FPGA

    Iirc, opencl requires a processor top control the system. Vhdl does not. OpenCL is a higher levelthan vhdl. So while you can probably Get a system up and running faster than vhdl, the vhdl solution...
  15. Closed: Re: How to increase the memory capacity of the IP core fifo_generator in Vivado 2018

    the ram size settings are set in the GUI when you generate the FIFO.
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    [SOLVED]Closed: Re: for generate with step other than one

    You cant.
    Indexing can be offset using maths
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    Closed: Re: Unknown xx req signal for NoC coding

    The "req" you show in the waveform is not the one you highlight in the code. Its the req inside the rr_arb_port_to_cpu instance
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    Closed: Re: FPGA ASIC gate count

    I also assume gate count can vary between technologies so isn't really a valid generic measure either.
  19. Closed: Re: Vivado Taking A Long Time To Run Synthesis & Implementation

    why is init outside the clock condition?> you're forcing the clock into logic, which is probably causing massive timing failures. Either put the init check inside the clock or remove it altogether.
    ...
  20. Closed: Re: Including VHDL libraries to add two signals

    Std_logic_arith and std_logic_unsigned are non-standard VHDL libraries. So I would recommend the use of only numeric_std, which is part of the VHDL standard.
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    Closed: Re: FPGA and processors working

    The Processor will be the "brains" and decision maker. The FPGA will be the data processor.
    FPGAs can easily handle and process 10s of GBits of data. The Processor will decide how the processor...
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    [SOLVED]Closed: Re: Writing to an output file in VHDL

    padding_length is an integer with no initial value. So will be set to -2^31+1 (same with padded_length). It means your message_length and padded_message and padding arrays have a 0 length (because...
  23. [SOLVED]Closed: Re: Range in parameter specification of FOR GENERATE must be static

    Imagine a generate loop is there to tell the designer how many chips to place on a circuit board.
    For one design it may have 6, for another it has 10 (as these may be set from generics)

    But it...
  24. Closed: Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

    The flow for asic is similar to fpga. You write rtl, synthesise, place, route, timing analysis. Asic has the additional steps of actually designing the chip, pin out, masks, emulation (often using...
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    Closed: Re: Circular buffer design

    1. Your counter has 1504 bits, meaning it can count from 0 to 2^1504. COunting to 1504 only requires 11 bits, so the counter should be



    signal packet_count : unsigned(10 downto 0) := (others =>...
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