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  1. Closed: Re: Two questions about HDL designer - simulation and attributes

    To me you should be concentrating on the synthesis warnings and determine why the FSM current_state (flip-flops) are getting removed. Registers should never be removed unless they reduce to a...
  2. Closed: Re: Can IP(Intellectual Property) open source, what does good business model?

    There are also a number of the more complex cores written by companies advertising their expertise, if you go to the website of the company submitting the core you find they have a bunch of other...
  3. Closed: Re: Two questions about HDL designer - simulation and attributes

    Add signal tap after the design is implemented (i.e. synth+par) The flip-flops for the FSM will exist in the routed design.

    Either that or instantiate the Signal Tap (assuming Intel/Quartus allows...
  4. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    I'm more inclined to believe you didn't follow what I wrote about above.


    I've used VHDL for decades and I've never needed to add a 1ns delay into a file reading process that loaded an array. Yes...
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    Closed: Re: Implementation of ADC

    Do you understand the difference between analog and digital signal? A Xlinx FPGA is a digital device it works with two voltage states to do something. It can't use analog signals to suddenly work as...
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    Closed: Re: parameterized MUX implementation

    Same way as a mux, if you implemented it with max width buses and index the packed array output to select where the input is routed.
  7. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    You did not implement option #1. Your array is already defined in the first line with the type declaration and it is set to 2001 entries.

    If your file is 5000 lines then your filling of the array...
  8. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    That is how you would use access the ROM, as both Xilinx and Altera have to have a clock to their block RAMs. That code lacks any code for an init_rom function to initialize the ROM, which is in the...
  9. Closed: Re: Finding certain string in file using bash shell scriot

    It also looks like the value may be on the next line which the line continuation is denoted by "*+". See lines 7 & 8.

    I think I would write a script with Python, Perl, Ruby, whatever than use...
  10. Closed: Re: What is the vhdl equivalent of "initial begin" to initialize a ROM.

    For both Xilinx and Altera the bitstreams include all the bit locations of the block RAMs in the devices. Specifically that is how Xilinx updates a bitfile with the software program for an embedded...
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    Closed: Re: parameterized MUX implementation

    This is possible using a packed array for the inputs and a parameter to define the number of input ports. Synthesis will work with such an array (at least Vivado synthesis and the newer version of...
  12. Closed: Re: Mains leaking currents causing problems in my house

    This alone would make me move out of that apartment and find another where the owner doesn't want their tenants to get electrocuted by 230V.


    You are suggesting the wrong person should do this....
  13. Closed: Re: Problem calling a function from my vhdl project in Vivado.

    Good grief, why are you copying Verilog directly to VHDL...
    If you use VHDL arrays for the tables then you don't need to do all that ugly indexing and bit slicing to return the data.


    your...
  14. Closed: Re: What is the future of Boolean algebra-based languages and methodologies?

    Out of everything one takes from this thread...
    This is the single most important gem in the thread. If the decision for tools is made by the "business" side of management you will be forever stuck...
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    Closed: Re: default statement in case

    ^
    This becomes very important for synthesis when you have an FSM that does not have a power of 2 number of states. FSMs with 2, 4, 8, 16 etc defined states will never lock up due to entering an...
  16. Closed: Re: Why should a solder joint be less than 110degc?

    Apparently you didn't read the entire sentence...



    Soldering isn't operating.

    The statement means the resistor film is in excess of 110C if the solder joints are at 110C.
  17. [SOLVED]Closed: Re: Which one is stronger? Arm cortex A9 in DE1-SOC or arm cortex A53 in Raspberry Pi

    Are you discussing an FPGA design with embedded software to run the FPGA design (Cyclone V DE1-SoC) or a software solution on a Raspberry Pi 3? If you are only using the Cyclone V's dual core A9 then...
  18. Closed: Re: Two questions about HDL designer - simulation and attributes

    I'm assuming you can create your own blocks in HDL Designer.

    How about trying instead making step 2 be:
    Step 2: create a entity with an input port with the signal you are trying to spy. Do the...
  19. Closed: Re: Determine whether a binary number is of power of two in verilog code

    Ah, sorry I was thinking you wanted power of 2 but not power of 2^0 for some reason (probably because of Tricky's comment). Never mind then extra & ~in[0] then your original post will correctly...
  20. Closed: Re: Determine whether a binary number is of power of two in verilog code

    Interesting that you are pointing this out to me as if I don't already know this solution. I have been discussing the question posted in #1 and the desire to translate it to Verilog. I was also...
  21. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    I merged two separate threads. It's obvious the first post was about trying to read the data file. The second post (which was in a new thread) was how they wanted to read the file but also serialize...
  22. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    Your loop only assigns the din_anc each clock cycle with a new value, there is nothing in the code to serialize the din_anc data.

    Did you even look at the example at the link I posted?

    You are...
  23. [SOLVED]Closed: Re: Reading from a TXT file to a 2d array in vhdl

    I'm not a VHDL expert so I can't be sure what the error means. But I do notice the if statement isn't doing anything as opening the file then checking for end of file is a rather useless check. The...
  24. Closed: Re: Variable Width CRC generator based on parameter "crc_poly"

    You keep changing the requirements...do you even know what you are supposed to design?
    * First you tell us you want to use a parameter (i.e. the parameter is set at compile time and can't be changed...
  25. [SOLVED]Closed: Re: Post place & route netlist simulation is failing although STA is ok

    What I would do in the future is take the signals between the memory model and the UUT and add delays to the signals passing to/from the memory model, these would be values you derive from the layout...
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