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Type: Posts; User: sherline123

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  1. Closed: Re: MOSFET linear and saturation region operation

    MOSFET acts like a switch and it is opened when vgs < vth but closed when vgs > vth.
    From simple MOSFET equation, ignoring body effect and etc.
    When Vds < vgs - vth it acts like a variable...
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    Closed: Re: Frequency Divider Circuit issue

    Series. Just like a NOR gate. This is async.
    So you want synch or async?
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    Closed: Re: Frequency Divider Circuit issue

    I don think it can work async. The waveform is correct corresponding to the schematic which is only can be reset when clk is falling edge.
    If you want something async, why don't you put a pmos on...
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    Closed: Re: Detect long string signal

    Low pass filter?
  5. Closed: Re: calculating or guessing the load of the circuit

    Can we just put an external resistor and measure voltage?
  6. [SOLVED]Closed: Re: Voltage to frequency converter - problem with simulation

    I assume when you say it doesn't work means your output is a flag dc signal?
    I suggest you to probe the in/output signals of each IC and check which signal is not in expectation for debug purpose.
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    Closed: Re: Frequency range selector

    Just my guessing.
    The clk pass through delay lines and sampled at the latch(i think it should be a flipflop instead of latch) of a refclk. With the refclk, we can get a code which representing how...
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    Closed: Re: Frequency Divider Circuit issue

    Actually do you know how to construct a clock/frequency divider circuit?
  9. Closed: Re: HSPICE Optimization for non-monotonic function

    Yes. I did go through HSPICE documents. But seem like it takes bisec method which might not suitable for a nonmonotonic function.
    Could you provide me with some examples?
  10. Closed: Re: HSPICE Optimization for non-monotonic function

    Sorry. I am new to this.
    I only tried with bisec method before.
    Random optimizer is it monte carlo?
  11. Closed: Re: HSPICE Optimization for non-monotonic function

    Hi, can provide more infos about this?
    I am new to this random optimizer. Thanks
  12. Closed: HSPICE Optimization for non-monotonic function

    Hi,

    Is it possible to use HSPICE optimization for a non-monotonic function?
    I am planning to do some optimization by sweeping all values within limits and find the best results.
  13. Closed: Re: Measuring a voltage that is higher than supply voltage

    voltage divider + ugb .
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    Closed: Biasing folded cascode opamp

    Hi,

    When we biasing for folded cascode opamp, normally we will make the current MN3 = MP1 + MP7
    But I saw some design actually make the sinking current of MN3 slight higher than current passed...
  15. [SOLVED]Closed: Re: Problem related to monte carlo simulation

    I am sorry but is what is WAT?
  16. [SOLVED]Closed: Re: Problem related to monte carlo simulation

    Since it is self-calibrated, why still need to run monte carlo? I thought it will calibrate until certain minimum offset meet before start operating?
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    Closed: Re: delay of inverters in series

    Maybe your metal RC is too worst and become the dominant.
    But you mentioned no change in the delay, is it totally no change or the change is very minimum?
    If totally no change, then I believe the...
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    Closed: Re: Shielding in IC analog layout design

    Normally I will shield it with vss as vss has stronger power grid.
    Some proposed to shield with 1 side Vdd and another side with Vss to reduce dcd
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    Closed: Re: Response of CMOS inveter in parallel

    If it is parallel and everything is indentical, it would just like you are sizing them 2x.
    But in real world, if you are putting 2 inverters, the input loading/output loading will never be...
  20. Closed: Re: Some questions about common drain amplfier

    In electronics, a common-gate amplifier is one of three basic single-stage field-effect transistor (FET) amplifier topologies, typically used as a current buffer or voltage amplifier **source from...
  21. Closed: Re: Some questions about common drain amplfier

    I am sorry but i thought common gate is the one called current buffer?
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    Closed: Re: Pull down behavior of an NMOS and PMOS

    You cannot know your output without the load. If your load is super high impedance, then little current is enough to drive it to Vdd.
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    Closed: Re: Analog Layout and Dummies

    I think only half dummies need to put in schematic. Fully dummies is already tied off and no need to put in schematic.
  24. Closed: Re: Perl/Python Scripting for Analog/Mixed Signal Design

    What do you mean by scripting for analog/mixed signal design?
    Is it scripting to help you process netlist or simulation results?
  25. Closed: Some questions about common drain amplfier

    Hi,
    I have some questions about common drain amplfier. Common drain is known as source follower/voltage buffer. But in large signal, I thought the highest output it could only be Vin - vth? Why it...
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