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Type: Posts; User: Chinmaye

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  1. Closed: Re: Converting verilog code into a symbol during AMS simulation

    How will i be able to split the pins? As in, I would like to have 4 pins by name in[0], in[1], in[2], in[3] instead of one pin in[3:0].
  2. Closed: Converting verilog code into a symbol during AMS simulation

    Dear all,
    I have a verilog code with input in[3:0] and output out[3:0]. When i try to create a symbol for it for ams simulation, it gives me only 2 pins. One pin for input, in<3:0> instead of 4 pins...
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    [SOLVED]Closed: AMS simulation of D-FF

    Hello all,
    I am unable to simulate D-flipflop properly in AMS. The input that i am giving is itself shown incorrect on the wave form window. I was able to simulate simple gates but find ing problems...
  4. Closed: ConnectLib files in ams simulation Cadence

    Hello all,
    I am trying to perform a test AMS simulation. After ADE launch, we go to setup->Connect rules. There i see a set of standard rules like 18_full_fast, 5_full_fast etc. All of these have...
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    Closed: Combine circuit and Verilog in Cadence

    Dear all,
    I have an ADC design in cadence virtuoso which is at transistor level. I would like to perform some operations on this output of the ADC. Is there anyway that i can write a verilog code...
  6. Closed: Re: Verilog-a code for differential amplifier

    Thank you. Shall try this.
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    288

    Closed: Re: Verilog-a code to latch analog voltages

    @cross() does not allow V() inside it. Hence it cannot be used
  8. Closed: Re: Verilog-a code for differential amplifier

    CMOS switch
  9. Closed: Verilog-a code for differential amplifier

    Hello all,
    Here is a simple verilog-a code for an amplifier with differential input and differential output. This works fine with resistors but if i try to use it with switched capacitor circuit, it...
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    Closed: Verilog-a code to latch analog voltages

    Dear all,
    I am trying to model analog latch in verilog-a but have been unable to do it. The requirement is as follows
    It is required to sample an analog value at positive clock cycle of CLK2 and...
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    Closed: Generate pulses of different widths

    Hello all,
    I would like to generate pulses of different widths at different instances of time in cadence virtuoso. How can it be done?
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    Closed: Warnings in nano route in innovus

    Hello All,
    I get this warnings while Nano Route. Due to these warnings, routing is not happening. Any idea how they can be resolved?

    #WARNING (NRDB-2040) Rule LEF_DEFAULT doesn't specify any...
  13. Closed: ramp generation using switched cap integrator

    Hello all,
    I am generating a ramp from 0 to 1V with 10mV steps using a differential switched cap integrator. But my requirement is to generate a ramp from -0.1V to 0.9V. How will I be able to...
  14. Closed: Re: Convert ITF file to ict for captable generation

    Sir, What is a linux binary file? Could you please explain more on this? Also is it possible to create layouts in innovus, without using captable files?
  15. Closed: Re: Convert ITF file to ict for captable generation

    How does the utility look like? Does it have any extension?
  16. Closed: Convert ITF file to ict for captable generation

    Dear all,
    I want to convert itf file to ict file and use it for captabl generation. How can it be done?
    The following link provides commands to do it. But again i do not understand that....
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    Closed: Very accurate analog comparators

    Any leads on how to go about building an analog comparator that can detect signals even with 20mV difference?
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    Closed: Re: Saving the layout in innovus

    Thank you sir. I was able to generate the gds file using the command stream out. But when i use the same .gds file to generate layout in virtuoso, there are lots of missing layers and it looks...
  19. Closed: Re: what is the bandwidth achieved for the given configurations

    For s single stage, Gain * Bandwidth product is constant. Gain of triple cascode >cascode > common source. Hence Bandwidth of Common source > cascode> triple cascode
  20. Closed: Re: MOSFET linear and saturation region operation

    MOSFET behaves like a resistor in linear region with resistance = 1/(un*cox*(W/L)*(Vgs - Vth)) for small values of Vds.
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    Closed: Re: Saving the layout in innovus

    Yes sir. The log file does not show any error. Attaching the log file for reference. Could you please let me know if there are any commands that can be run to get the gds file instead of GUI?
  22. [SOLVED]Closed: Re: Error during clock tree synthesis in innovus

    This problem automatically got solved when i run nanoRoute command
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    Closed: Re: Saving the layout in innovus

    I am trying the option save-> gdsii. But cannot find a gds file in any folder. I am attaching the screenshot of the steps i am following to get gds file. Please let me know what i am missing. Plz...
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    Closed: Saving the layout in innovus

    Dear all,
    I have generated a layout in innovus for a sequential circuit. I have run all the steps including routing. Now i would like to save the layout and would like to access it again further. I...
  25. [SOLVED]Closed: Error during clock tree synthesis in innovus

    Dear all,
    I am new to innovus tool. I get this error during clock tree synthesis.
    ERROR: (IMPCCOPT-2215): The route/traversal graph for net 'clk' is not fully connected
    What does it mean and how...
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