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  1. Replies
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    Closed: HBM Model Simulation ESD - TINA TI

    Hi
    I am trying to understand the behaviour of Human Body Model simulation circuit in Tina TI.

    I found a circuit provided by TI (as below)
    154845

    I ran a transient analysis of this and got the...
  2. Closed: Re: Transimpedance and Potentiostatic circuit oscillations

    Yes you were absolutely correct. It was assembly issues that was causing these problems. I saw the board under the visual inspection camera and it was awful. Dry joints, too much flux. I now repaired...
  3. Closed: Re: Transimpedance and Potentiostatic circuit oscillations

    OK i took some traces.

    I first built Potentiostatic circuit only. The OPAMP used in this case was SOT-23 LPV821

    154106

    I used R13 & R14 as 11K & 13.3K respectively. I used 10uF cap as C1.
    ...
  4. Closed: Re: Transimpedance and Potentiostatic circuit oscillations

    Has anyone here had any such issues with Rail ceramic caps going low impedance when plugged in circuit and then back high impedance when voltage is taken off? Or if it is happening because the Opamp...
  5. Closed: Re: Transimpedance and Potentiostatic circuit oscillations

    I have done three different revisions on PCBs just to tackle this issue. The board also have other digital circuit like uC and memory etc. But then I decided just do a standalone board for this. ...
  6. Closed: Re: Transimpedance and Potentiostatic circuit oscillations

    Yes I originally started with using 10R Rload from your mentioned alpha sense note but it was oscillating.
    I was then advised to use 100R to 470R
    I have used high value bypass caps like tantalum...
  7. Closed: Transimpedance and Potentiostatic circuit oscillations

    Hi
    I am trying to interface an O2 Electrochemical sensor on my board.

    I have used potentio-static & transimpedance amplifier configuration.

    I have tried to use what I found in number of...
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    Closed: TI TINA simulation with AD8603 over voltage not picking up

    Hi I am new to TINA TI simulation world. I used one of their example circuit 0-10V @ 10mA DAC Interface Circuit ( see attached)

    153720



    I noticed that original OPAMP in the example circuit...
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    Closed: Qi charger power (Watts) rating

    Hi

    I am bit confused about the Wattage rating of Qi (wireless chargers)

    e.g., they come in different flavours as 1W / 5W/ 7.5W / 10W etc

    I know P = V x I

    But, I am struggling to...
  10. Closed: Inductance meter (LCR meter) for Qi receiving coil measurement

    Hi

    I am working on a wireless power receiver design (Qi compliant)

    As part of design I need to measure Inductance of my receiver coil @ 100kHz / 1Vrms (using the test setup as explained on...
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    [SOLVED]Closed: Re: ASMD Chart decision boxes for OR condition

    Thank you very much. I did not realise that 'state blocks' and 'Decision blocks' could have multiple exit and entry points respectively.

    I was working on the assumption that:

    State block could...
  12. Replies
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    [SOLVED]Closed: ASMD Chart decision boxes for OR condition

    Hi

    I am trying to prepare an ASMD chart for my VHDL design.

    My question regarding ASMD decision boxes:

    Could we have multiple conditions to be checked mentioned in single decision box?

    I...
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    Closed: Re: Parking lot occupancy counter State Diagram

    Thanks, that worked with two states taken out
  14. Replies
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    Closed: Re: Parking lot occupancy counter State Diagram

    Fantastic that works :) Thank you very much. Now I am going to look into following advice as it looks like it would help me to reduce the number of states
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    Closed: Re: Parking lot occupancy counter State Diagram

    What do you mean by 'registered all the outputs'?

    Do you mean combine the
    process (clk, reset) & process (state_reg, a_frnt, b_bck, ms_tick)

    to something like this:

    process (clk, reset,...
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    Closed: Re: Parking lot occupancy counter State Diagram

    Ok I think I am still confused here.

    Here is my code:



    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    -- Uncomment the following library declaration if using
  17. Replies
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    Closed: Re: Parking lot occupancy counter State Diagram

    I have done the following mod:

    152247

    Where I now generate the output ticks when changing the state from State-3 to State-0 OR State-7 to State-0.

    But problem I have is that depending upon...
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    Closed: Parking lot occupancy counter State Diagram

    Hi I am working on this problem using VHDL design

    It requires two inputs as two sensors (A & B) (as shown in the pdf attached)

    152244

    It has two outputs as ENTER_CAR & EXIT_CAR. They need to...
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    [SOLVED]Closed: Re: Time multiplexing with LED

    Thank you very much for your help



    Yes you are absolutely correct. & I usually try doing this. But two issues that I struggle to deal with:

    First -- on anything that I have not got...
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    [SOLVED]Closed: Re: Time multiplexing with LED

    Thank you for your help.



    These signals are defined in disp_mux.vhd.

    My test bench is for disp_mux_test.vhd

    How would you normally map the testbench ports to map to the signals in...
  21. Replies
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    [SOLVED]Closed: Time multiplexing with LED

    Hi
    I am working my way through FPGA prototypes with VHDL examples’ book by Pong P chu. I am trying to simulate the design in Listing 4.15 (dis_mux_test)

    Which is as below:

    ...
  22. Replies
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    [SOLVED]Closed: Re: VHDL coding Status register read problem

    Ok I have modified my code now. & I believe that my PWM outputs are now working as I wanted them (for now)

    See picture below from my simulation:

    151990

    So I have,
    when my main counter...
  23. Replies
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    [SOLVED]Closed: VHDL Counter Clock issue

    I am trying to do VHDL design to generate PWM outputs.

    The period, On time & Off time for the waveforms would be programmed into the FPGA registers by a micro controller in real time (using its...
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    [SOLVED]Closed: Re: VHDL coding Status register read problem

    Thank you very much for your help.

    In fact, ISE generated some warnings during Synthesis for this issue but No errors. I have now modified the code and got rid of those warnings.

    It still did...
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    [SOLVED]Closed: Re: VHDL coding Status register read problem

    Thanks for the feedback.

    Few questions as I am confused here


    I appreciate that there is no single flip-flop that has both rising & falling edge clocking. But if we have condition like this...
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