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Type: Posts; User: dick_freebird

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  1. Closed: Re: Netlist is different between schematic and layout

    Regular FETs don't have a difference between D-S and
    S-D electrical behavior. Some asymmetric types do -
    drain-extended and LDMOS for example. LVS rules
    will have "S/D swap" switch which allows...
  2. Closed: Re: Phase detector with synchronous logic (FPGA)

    Can you just get the two positive-going zero crossings
    and run a timer, and then do the arithmetic? Seems like
    a 800MHz clock would get you better than 1 degree
    resolution. Accuracy might have...
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    Closed: Re: RF Switch with diode

    I believe you want a high-Q shunt C at the PIN diode
    cathode, to signal ground. Otherwise the circuit as
    drawn will "kill" the PIN diode C(fwdBias) inductively.

    For the kind of wattage you are...
  4. Closed: Re: Switch size in a resistive trim network ?

    I recommend considering the resistor segment and the switch
    as the resistor-bank "unit cell", and repeating this as you make
    series / parallel arrangements.

    Switch Ron vs common mode is a...
  5. [SOLVED]Closed: Re: solution to over current / protection circuit

    Consider IC "load switch" products, which have the
    pass device (with or without features like short
    circuit protection and inrush control, which you may
    want or not) and the logic interface all...
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    Closed: Re: Open Collector design Question

    You might be able to make a cascode open-drain stage
    if you have a HV well or a SOI tub to put the guard NMOS
    into. Tie its gate to VDD, source to the "master" switch
    NMOS below, drain is the...
  7. Closed: Re: Linux Command to Copy Multiple Files?

    foreach x(*)
    mv $x $x.docx
    end
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    Closed: Re: Reference buffer for BGR

    The buffer will contribute offset and gain errors to the
    reference voltage. However it can also be a place to do
    voltage trimming (presuming you can stand the current
    taken by a resistor network)...
  9. Closed: Re: Linux Command to Copy Multiple Files?

    If it were me, I'd get the file list as plain text from
    "wherever", and edit it into a shell script with vi / vim.
    Then run it.

    :1,$s/^/cp \/home\/user\/Desktop\/temp\/rubric.docx &/

    would...
  10. Closed: Re: Different transistor orientation in different matched MOS array

    It depends -what- is to be matched.

    If you feed array A and array B identical current bias
    then they don't care about orientation, local match
    is still good and current mirror behavior is fine....
  11. Closed: Re: How D flip flop can hold output until next clock cycle when it is level firered.

    Specifically, you (OP) show first a flip-flop in toggle
    feedback configuration, but then you show a half-
    latch (half of a D FF) in the same feedback config
    and expect it to work the same (it...
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    Closed: Re: high speed latch problem

    There is no plot of CLK_minus, what is it doing?

    CLK is not ppropriate as a CML input, you cut off the input
    pair hard every time you put it to zero. If CLK_minus does
    the same then you may...
  13. Closed: Re: How can I know the location of an UHF passive tag?

    Triangulation by multiple antennae or by moving RX
    position / orientation, looking for field strength?

    Tags don't know where they are, themselves. You
    are asking for direction- and...
  14. Closed: Re: How to find Vec of an active mode pnp

    Vce ought to be one of the reported OP results.

    Getting to that, depends on which simulator / GUI or
    command line interface.

    In ngspice I'd just run an OP and then "show q" and
    pick out the...
  15. [SOLVED]Closed: Re: ESD Circuit protection against electrostatic painting

    You would think that powder-coating the terminals would be bad,
    ESD or no.

    Maybe an answer would be using a conductive-material connector
    "filler plug" which could at least short the pins...
  16. Closed: Re: why is write delay low for 6T SRAM cell compared to 8T SRAM cell ?

    Assuming that they are on the same technology (which
    you do not state) there's just the extra read-path load
    requiring additional slew time on write, to get to the
    positive feedback tipping point...
  17. Closed: Re: How to choose optimal wire width of spiral coil to attain high q factor?

    A problem with spiral inductors is that when you increase
    W, looking for Q, you also force the L to grow somewhat
    for the same core area. So you won't get the W2/W1
    improvement in series R, that...
  18. Closed: Re: Accurate mains zero cross detector circuit without optocoupler

    Decades ago we used an integrator (for phase shift,
    we wanted a 90 degree timing pulse for SCR motor
    control firing) followed by a comparator. For a zero
    crossing you could just use a single...
  19. Closed: Re: Circuitry to make Paralleled Buck converters share current.

    Depending on the PWM controller you may find it easy
    to gang parallel converters with decent load sharing.
    Or not.

    If the error amp feeds the current compare in a
    current mode control PWM then...
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    Closed: Re: Properties of MIM capacitors

    You must not have been looking at the documentation
    from any foundry that offers MIM caps on their process
    flows.

    Looking at generic information isn't all that helpful
    because the MIM cap...
  21. Closed: Re: Remove glitches in output frequency of ring oscillator

    Color-on-black is the Cadence default and simple screen
    shot is what you see. When I do "paper" documentation
    I always turn them to black-on-white, but that's another
    4 clicks per pic.
  22. Closed: Re: Remove glitches in output frequency of ring oscillator

    Those aren't "glitches". They are full scale, fully settled reswitch
    (chatter). Moreover it appears repetitive.

    Your RO should have one and only one cycle of a standing wave.
    Stop the cycle and...
  23. Closed: Re: LLC converter vs Dual cascaded Buck….1000V to 48V at 500W output…no isolation ne

    To the point of no 1kV models, the next page I hit
    on my way out from edaboard showed me this:

    https://www.eeworldonline.com/e-commerce-site-offers-designers-device-models-on-demand/
    ...
  24. Closed: Re: LLC converter vs Dual cascaded Buck….1000V to 48V at 500W output…no isolation ne

    Have you considered the "solid state transformer" as
    Stage 1? That being a fixed-duty buck with no control
    loop at all? These can be made pretty efficient and
    no compound-converter-stability...
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    Closed: Re: SMPS for 5000W can be a Full Bridge

    Ridley is still very active and putting out new material.

    He has a Facebook power supply design group that you
    could join (I think - sort of a velvet-rope deal for many
    "interest" groups, so...
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