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Type: Posts; User: FlyingDutch

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  1. Closed: Re: windows programming to create hex for microcontroller

    Hello,

    you can write a program in C for microcontroller(skeleton), and Windows application - code generator (for example in C# using Visual Studio) which generates code also in C for...
  2. Closed: Re: Wifi audio hub.Multiple users will be able to listen using any earbuds or headpho

    Hello,

    nowadays each of us wanna design a SoC, me too :wink:. But I am aware that this is next to impossible to accomplish.
    Why? Because it is extremely complex task. It needs enormous knowledge...
  3. Closed: Re: TC34725 i2c color sensor not working without any error (basys3 vhdl)

    Hello,

    are you sure that this I2C addres is actually proper address:


    --The address of the TCS34725. This device has only one possible address,
    --so we won't genericize it.

    constant...
  4. Closed: Re: TC34725 i2c color sensor not working without any error (basys3 vhdl)

    Hello,

    if I have been in your position I checked first how this sensor is behaving using Arduino. It is very easy to write a skech wihch can comunicate by I2C with sensor. I assume that you are...
  5. Closed: Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

    Hello guys,

    I am a bit confused again. Could you answer my additional questions:

    1) Software tools for designing ASICs also use Verilog?

    2) These tools can use "switch-level" descriptions...
  6. Closed: Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

    Hello,

    I was surprised than I red about this level of abstraction in context of designing FPGAs in Verilog. This coures is a shortcut from a lectures of "Programable devices" subject in one of...
  7. Closed: Re: how to check a register value is 1 using verilog?

    Hi,

    I mean that "==" operator in case of registers is comparing them bit by bit (also "===" operator that aditionaly comparing bit by bit "x' and "z" states).

    Regards
  8. Closed: Re: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

    Hello,

    I mean for example simulation of capacitive network, like on this screenshot:
    152830

    The course I am reading is concerning FPGA designing using Verilog, but maybe this topic is related...
  9. Closed: Verilog "Switch-level" of circuit description has it equivalent in VHDL?

    Hello,

    I am learning myself Verilog (in which I haven't big expierience). During studying tutorial concerning Verilog features I encountered some topics concerning "Switch-level" of circuit...
  10. Replies
    3
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    642

    Closed: Re: VHDL the maximum width of databus

    Hello,

    the one biggest I saw was 256-bit wide.

    Regards
  11. Closed: Re: fpga spartan 6 io ports are no longer working

    Hello,

    in order to someone can help you you have to give more details:

    1) Type and link to FPGA bord you are using for this code
    2) JTAG programer: is it internal on-board or external (if yes...
  12. Closed: Re: Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    Hello,

    I have got an answer for my question about internal BrieySoC DDR memory controle on Telegram forum: Sipeed.io . Here is an answer I've got:



    I have SDRAM memory controller working...
  13. Closed: Re: Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    Hello,

    I made few changes to my project, and fixed few issues. The list of changes is here:

    1) Changes in buffering clock signals (PLL) instance CLKWizard

    2) Added input buffer (IBUFG) for...
  14. Closed: Re: how to check a register value is 1 using verilog?

    Hello,

    check this link:

    https://stackoverflow.com/questions/5927615/what-is-the-difference-between-and-in-verilog

    Regards
  15. Closed: Re: Spartan6 (ISE 14.7) how to generate differential clock?

    Hello,

    I placed in my Verilog code OBUFDS instance like that:




    wire CLOCK_OUT_P,CLOCK_OUT_N;
  16. Closed: Re: Spartan6 (ISE 14.7) how to generate differential clock?

    Hello,

    I thought that differential clok is consisted from two signal lines. Signal on second line is square wave shifted in phase for 180 degrees in relation to signal on first line.
    I know that...
  17. Closed: Spartan6 (ISE 14.7) how to generate differential clock?

    Hello,

    I would like to ask: How to generate differential (two lines) clock from "normal" clock (one line). The clock frequency is 100 MHz. Project is written in Verilog and I am using
    "ISE...
  18. Closed: Re: Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    Hello,

    I corrected my design and now there aren't erros - implementation ends without errors. The design is still not finished - I didin't mapped all signals for DDR controler (ucf file). I am not...
  19. Closed: Re: Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    This is because of that design is not finished by me and I am aware of it. I would like to ask earlier if the "DDR memory controler" in oryginal design entity Briey.v is complete? I assumed that it...
  20. Closed: Re: Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    Hello,

    I altered my project: all needed clock are generated by one entity named CLKGEN. I also added an "IP core" (Select I/O wizard) width bi-directional buffer - entity named DDRDataBuffer.
    See...
  21. Closed: Re: Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    I will implement such buffer. Thanks for hint.

    Regards
  22. Closed: Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    Hello,

    I am trying to launch one of implementation of RISCV CPU called Briey. Here is link to this project:

    https://github.com/SpinalHDL/VexRiscv

    I just modified this project (generated with...
  23. Replies
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    2,535

    Closed: Re: Inheritance in HDL languages

    Hello,

    I realized that SpinalHDL has full inheritance because it is based on Scala programming language. Drawback is that SpinalHDL is not direct tool for syntessis of FPGA, it just generate...
  24. Replies
    7
    Views
    2,535

    Closed: Re: Inheritance in HDL languages

    Hello,

    thanks for quick answer. I have module (Verilog) with soft-processor (Briey SoC - RISC-V). This module requires two clocks - one for AXI bus and second for VGA. I would add two PLLs clocks...
  25. Replies
    7
    Views
    2,535

    Closed: Inheritance in HDL languages

    Hello,

    I am wondering if there is any form of inheritance in VHDL or Verilog. I am not very expierienced user of these languages, but several times in my projects (VHDL mostly) I noticed that...
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