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  1. Replies
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    Closed: Re: UART Problem on CPLD c-m240 board

    I threw it into Modelsim and used force statements to generate the clock, start, and forced a reset to the sub-module reset and it seemed to be running with a 8-bit, no parity, 1 stop bit mode (I...
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    Closed: Re: Problema para crear coregen en ISE 14.5

    Are you using the webpack version of ISE? ISE webpack doesn't support any Virtex parts. I also don't think ISE uses the Vivado licensing (in case you only have Vivado licenses, I can't verify as the...
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    Closed: Re: AXI arvalid signal issue

    Your implementation of an AXI slave may behave this way but this is not part of the AXI specification. You should avoid ambiguities in your comments that mix specification and specific implementation...
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    Closed: Re: AXI arvalid signal issue

    For slaves that support arlen >1 i.e. bursts, the slave must perform address increments, the master only sends the start address of a burst.

    If you make the master do single transfers you lose a...
  5. Closed: Re: Laptop RAM upgrade (new RAM doesn't work in RVS slot, but works in STD slot)

    Then maybe you have RAMs with the wrong CL. If you have the wrong CL they may not work correctly.
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    Closed: Re: AXI arvalid signal issue

    Thanks Tricky forgot they changed that between AXI3 & AXI4, haven't had to write code for either interface for over 2 years, been stuck using APB and AHB.
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    Closed: Re: AXI arvalid signal issue

    Pending transactions means you can send multiple transactions not expecting the return reads to show up before the next transaction is completed. This can also result in out of order transactions,...
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    Closed: Re: AXI arvalid signal issue

    else if(i_axi_arready && o_axi_arvalid && o_axi_rready)

    This will not work in all situations. ARREADY and ARVALID don't have to be high when RREADY is high, they are from different channels.
    ...
  9. Closed: Re: External Ethernet Microcontroller or ZYNQ

    Doesn't matter, which way you do it. Either way the performance (i.e. the maximum payload bps you can transfer) is dependent on whether or not you can keep up with the data transfer to the MAC...
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    Closed: Re: AXI arvalid signal issue

    You clearly are not understanding the AXI spec and seem to be trying to read between the lines. There are only a couple of places that can be misinterpreted and those are on rarely used features from...
  11. Closed: Re: System Verilog error VLOG-13069 from Questasim with unpacked array

    Insisting something is right when it doesn't compile should give them a less than 0 guru score IMO.
  12. [SOLVED]Closed: Re: Random Led Blinker on DE10-lite FPGA board: [0-7]LED

    I don't get why you have the rnd signal set to be 10-bits it only has 8 states so only needs 3-bits. I would get rid of the inversion of the LED_status assignments and just assign a 1'b1 to the...
  13. Closed: Re: Using generate and for loop to index signal name

    Do you compete in Verilog obfuscation competitions?

    Stuff like this is going to reduce maintainability, which to me is far more important than trying to avoid typing something out explicitly.

    I...
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    Closed: Re: Understanding Skid Buffer Mechanism

    Impossible to merge at this point, the thread would become unreadable due to the interleaving of posts that are unrelated to each other.

    - - - Updated - - -

    One of the issues with promach's...
  15. Closed: Re: System Verilog error VLOG-13069 from Questasim with unpacked array

    dave_59 in post #2 mentioned the indices were swapped, you must have misread the line.
  16. Closed: Re: System Verilog error VLOG-13069 from Questasim with unpacked array

    No the numbers just represent the bits for a specific array entry they aren't hex digits. I though the widths of the bits and the descriptions would be enough to be clear what I was showing, I guess...
  17. Closed: Re: System Verilog error VLOG-13069 from Questasim with unpacked array

    using the following example arrays:

    logic [3:0] bt1[7:0];
    logic [3:0][7:0] bt2;
    logic [7:0][3:0] bt3;


    The bit definitions of the arrays are:
  18. Closed: Re: Problem in reading W5300 registers with Spartan6

    Using a DCM is better as the tools will place the clocks on dedicated routes from the DCM to the global buffers. Also use the global buffer output as the feedback path you can remove the clock...
  19. Closed: Re: Laptop RAM upgrade (new RAM doesn't work in RVS slot, but works in STD slot)

    std_match, When I did a quick search yesterday I noticed that there was conflicting information on the RAM required (DDR3L or DDR4) for a 15-ay013dx, so they probably didn't check their HP...
  20. Closed: Re: Problem in reading W5300 registers with Spartan6

    Where is your testbench? Did you just compile this code and try it on hardware without running it in a VHDL simulator?

    One thing I do notice, you are using clock dividers, which are not a good...
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    Closed: Re: AXI arvalid signal issue

    That doesn't look right, any of the valid signals (from the master) should not be using the ready (slave) status to determine if the valid should be asserted.

    The de-assertion of valid does look...
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    Closed: Re: Recommendations for Beginner

    Tasks are only slower in Vivado if you don't script the flow or use the Tcl command line to do everything. Vivado when run exclusively using the GUI, unloads the database after each step. This...
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    Closed: Re: how to generate 4MHz clock from 2 MHz clock.

    Must be a Xilinx part (MMCM/PLL), but can't tell which one as more than one of the families has that primitive. Though it can be narrowed down with the OP's statement that the wizard says the FPGA...
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    Closed: Re: Recommendations for Beginner

    I think it's an opinion based on smaller parts, for the largest parts in the Xilinx family ISE was very slow due to the extremely large memory requirements and the database design that wasn't very...
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    Closed: Re: SERDES termination methods

    If you are looking for the standard. SERDES uses CML or Current Mode Logic. The term SERDES describes the upper layer protocol for the Serilaizer and Deserializer.

    You can have SERDES that uses...
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