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Type: Posts; User: dick_freebird

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  1. Closed: Re: Why set_max_fanout constraint in design compiler ?

    Every library has timing models derived from some
    bounding conditions including min and max load.
    The fanout you specify, or the fanout that your local
    setup defaults to, must respect that "box"...
  2. Closed: Re: Rise times and fall times of fast transistors seem way too long

    fT of an unloaded transistor, or one in a 50 ohm ideal
    test setup and rise/fall times with a spec load, 10-90%
    are not at all the same condition.

    Fall time is drive current and (load+Miller)...
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    Closed: Re: would an engineer use this equation?

    Here, it is "transformer". But in other discussions it
    could as well be transistor or transmitter, depending
    on context.
  4. Closed: Re: Which CMOS Transistor is suitable for Power amplification (ranging form 7MHz ~ 9M

    There is no CMOS transistor, singular.

    Generally NMOS has superior Ron*Coff product which
    is a figure of merit for switch and switched-mode PA
    applications.

    But you don't say whether this is...
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    Closed: Re: would an engineer use this equation?

    A real engineer skilled in the art would consider this
    a very rough guide and from there, move on to more
    analysis and characterization. The Ridley power supply
    group on F*c*book currently has a...
  6. Closed: Re: How to get the operating temperature ( case temperature)

    If you're of an experimental mood, you can use input
    or output ESD diodes, or possibly active pin attributes
    as a temperature proxy; a little oven time and some
    data points for diode Vf@If, and...
  7. Closed: Re: Excessive space needed for Transient analysis Cadence

    "keep all" / "save all" collects a ton of data that you
    probably do not care about. You can save only the
    explicitly-cared-about vectors.

    If you only care about the last N cycles of that...
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    Closed: Re: How to glue a heat sink on a IC

    "Arctic Silver" epoxy is (or was) popular for PC CPU /
    GPU heat sink attach.

    What kind of package and how the heat flows, may
    be a concern. Putting the heat sink on a plastic package
    that has...
  9. Closed: Re: Netlist is different between schematic and layout

    Regular FETs don't have a difference between D-S and
    S-D electrical behavior. Some asymmetric types do -
    drain-extended and LDMOS for example. LVS rules
    will have "S/D swap" switch which allows...
  10. Closed: Re: Phase detector with synchronous logic (FPGA)

    Can you just get the two positive-going zero crossings
    and run a timer, and then do the arithmetic? Seems like
    a 800MHz clock would get you better than 1 degree
    resolution. Accuracy might have...
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    Closed: Re: RF Switch with diode

    I believe you want a high-Q shunt C at the PIN diode
    cathode, to signal ground. Otherwise the circuit as
    drawn will "kill" the PIN diode C(fwdBias) inductively.

    For the kind of wattage you are...
  12. Closed: Re: Switch size in a resistive trim network ?

    I recommend considering the resistor segment and the switch
    as the resistor-bank "unit cell", and repeating this as you make
    series / parallel arrangements.

    Switch Ron vs common mode is a...
  13. [SOLVED]Closed: Re: solution to over current / protection circuit

    Consider IC "load switch" products, which have the
    pass device (with or without features like short
    circuit protection and inrush control, which you may
    want or not) and the logic interface all...
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    Closed: Re: Open Collector design Question

    You might be able to make a cascode open-drain stage
    if you have a HV well or a SOI tub to put the guard NMOS
    into. Tie its gate to VDD, source to the "master" switch
    NMOS below, drain is the...
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    Closed: Re: Linux Command to Copy Multiple Files?

    foreach x(*)
    mv $x $x.docx
    end
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    Closed: Re: Reference buffer for BGR

    The buffer will contribute offset and gain errors to the
    reference voltage. However it can also be a place to do
    voltage trimming (presuming you can stand the current
    taken by a resistor network)...
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    Closed: Re: Linux Command to Copy Multiple Files?

    If it were me, I'd get the file list as plain text from
    "wherever", and edit it into a shell script with vi / vim.
    Then run it.

    :1,$s/^/cp \/home\/user\/Desktop\/temp\/rubric.docx &/

    would...
  18. Closed: Re: Different transistor orientation in different matched MOS array

    It depends -what- is to be matched.

    If you feed array A and array B identical current bias
    then they don't care about orientation, local match
    is still good and current mirror behavior is fine....
  19. Closed: Re: How D flip flop can hold output until next clock cycle when it is level firered.

    Specifically, you (OP) show first a flip-flop in toggle
    feedback configuration, but then you show a half-
    latch (half of a D FF) in the same feedback config
    and expect it to work the same (it...
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    Closed: Re: high speed latch problem

    There is no plot of CLK_minus, what is it doing?

    CLK is not ppropriate as a CML input, you cut off the input
    pair hard every time you put it to zero. If CLK_minus does
    the same then you may...
  21. Closed: Re: How can I know the location of an UHF passive tag?

    Triangulation by multiple antennae or by moving RX
    position / orientation, looking for field strength?

    Tags don't know where they are, themselves. You
    are asking for direction- and...
  22. Closed: Re: How to find Vec of an active mode pnp

    Vce ought to be one of the reported OP results.

    Getting to that, depends on which simulator / GUI or
    command line interface.

    In ngspice I'd just run an OP and then "show q" and
    pick out the...
  23. [SOLVED]Closed: Re: ESD Circuit protection against electrostatic painting

    You would think that powder-coating the terminals would be bad,
    ESD or no.

    Maybe an answer would be using a conductive-material connector
    "filler plug" which could at least short the pins...
  24. Closed: Re: why is write delay low for 6T SRAM cell compared to 8T SRAM cell ?

    Assuming that they are on the same technology (which
    you do not state) there's just the extra read-path load
    requiring additional slew time on write, to get to the
    positive feedback tipping point...
  25. Closed: Re: How to choose optimal wire width of spiral coil to attain high q factor?

    A problem with spiral inductors is that when you increase
    W, looking for Q, you also force the L to grow somewhat
    for the same core area. So you won't get the W2/W1
    improvement in series R, that...
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