Search:

Type: Posts; User: ads-ee

Page 1 of 20 1 2 3 4

Search: Search took 0.06 seconds.

  1. Replies
    15
    Views
    2,661

    Closed: Re: E-mails about thread replies

    If you type don't instead for the "don-t" from the link it gets changed automatically back to don-t. So something changed between the other day and now for doing this character swap.
  2. Closed: Re: Parameterized register chain in Systemverilog

    I think I tried using a 2d for the parameter and it didn't work correctly (I don't remember exactly what was wrong, but I think the problem had to do with the instantiation of the module...it could...
  3. Closed: Re: Parameterized register chain in Systemverilog

    Try something like this


    parameter width_reg = 8,
    parameter number_of_regs = 4,
    parameter [width_reg*number_of_regs-1:0] default_value = {width_reg*number_of_regs{1'b0}}

    There may be a...
  4. Replies
    3
    Views
    332

    Closed: Re: Looking for lite synthesis software

    Tricky yosys doesn't generate Xilinx bit files. It doesn't do any place and route it is purely a synthesis tool and outputs EDIF with Xilinx library primitives for some Xilinx parts including Xilinx...
  5. Closed: Re: Implementation error (ERROR: Place: 1500) on ISE 14.5

    The errors mention RPM (Relative Place Macro or something like that). That means there are constraints on the placement of the I/O cells relative to other cells in the design. These are either from...
  6. Replies
    3
    Views
    997

    Closed: Re: UART Transmit issue with CPLD

    Run the code and the testbench in a simulator and observe in the waveform view what the design is doing and debug why it isn't doing what it was supposed to do. As you already have a testbench run it...
  7. Closed: Re: Verilog/SV: can assign + ternary produce latches?

    This is because Vivado and previously ISE weren't always that great at language compliance. Over the years I'd seen all kinds of strange behaviors.

    My recommendation is to only write code in...
  8. [SOLVED]Closed: Re: Vivado Synthesis failed with No errors or warnning

    As the file is just a bunch of instantiated components. I suggest instead of using positional port mapping to explicitly map the ports. I've seen Vivado and ISE before have issues with valid code...
  9. Closed: Re: Error: Identifier "ODDRE1" does not identify a component declaration.

    Thanks for pointing this out, I don't run VHDL simulations all that often so wasn't certain about the error message pointing to a missing library or component declaration.

    If you decide to run...
  10. Closed: Re: Error: Identifier "ODDRE1" does not identify a component declaration.

    If this purely a simulation issue, wipe out the entire simulation directory. I normally run Modelsim with a scripts. I usually have two different scripts, one to compile vendor libraries and one to...
  11. Replies
    15
    Views
    2,661

    Closed: Re: E-mails about thread replies

    These URLs are truncated with "-(Low[/url] Voltage Regulator)-do-you-have&goto=newpost" at the end instead of the [/url] after the newpost

    - - - Updated - - -

    FYI, I don't know if this is...
  12. Replies
    10
    Views
    1,131

    [SOLVED]Closed: Re: Device Support for MAX10 FPGA

    Download an older version of the tools that support the MAX10 part you are using. Vendors regularly end of life parts and those parts will no longer show up in their tools.

    Haven't used Intel's...
  13. Closed: Re: Verilog code for ring counter using "Genvar"

    The easiest way to look at a for loop is to unroll it manually to make sure you wrote it correctly


    for(i=0;i<N;i=i+1)begin
    dff inst_1(q_o[N-1],q_o[i],clk,rst);
    end



    dff...
  14. Replies
    3
    Views
    411

    Closed: Re: 100MHz SPI Clokck Generation

    You are using incorrect terminology in your posts, so your questions don't make any sense.

    What you have shown for your VHDL code is a simple divide by 2, 4, 8, and 16, with another divide by N/2...
  15. Replies
    8
    Views
    710

    Closed: Re: Artix7 XC7A100T BRAM Math

    He got that because they miscalculated the number of bits in the device.

    wrong 18KB (kilobytes) should be 18 Kb (kilobits)


    This calculates the number of bits for 270 8192-bit RAMs, which...
  16. Replies
    29
    Views
    1,663

    Closed: Re: what is slave address for ADC121C021

    Note I stated that


    Looking at the datasheet page 17 Figure 24 and the tables at the top of page 18. A pointer register value olf 0b00000000 points to the register called "Conversion Result",...
  17. Replies
    29
    Views
    1,663

    Closed: Re: what is slave address for ADC121C021

    The register definitions are clearly stated in the tables.
    The register structure is extremely simple it has a pointer register, which selects which register you will access.

    Procedure is:

    1....
  18. Replies
    29
    Views
    1,663

    Closed: Re: what is slave address for ADC121C021

    All the configuration register bit definitions for the device are described in the datasheet that you posted in #1





    They are doing this without hardware.
  19. Replies
    148
    Views
    9,179

    Closed: Re: AXI arvalid signal issue

    Posting that much code in a syntax window is ridiculous nobody is going to want to scroll through 1631 lines of code to look for one signal, that is not even in the posted code (I had to copy the...
  20. Replies
    11
    Views
    2,043

    Closed: Re: How do ESD monitors work ?

    It is interesting that the website the picture post is from is a website that has a description of the methods used to detect a person in the "loop"
    ...
  21. Replies
    12
    Views
    1,017

    [AVR]Closed: Re: Temprature sensors. LM35 vs MCP9700

    The other option to "calibrate" either of the parts is to use a reference like the digital sensor in the room as the "golden" reference and adjust the reading accordingly with an offset. This only...
  22. Replies
    12
    Views
    1,017

    [AVR]Closed: Re: Temprature sensors. LM35 vs MCP9700

    I don't see why there is anything wrong between the two, they are tracking very well.

    I just see a need for calibration being done on the sensor(s).
  23. Replies
    13
    Views
    1,486

    Closed: Re: Error :Syntax error near "module"

    they are equivalent, but I would suggest never writing stuff like this:

    if (not app_en = '1') and (not app_wdf_wren = '1') then
    state <= READ;
    end if;
    It doesn't follow a KISS rule.

    It...
  24. Replies
    13
    Views
    1,486

    Closed: Re: Error :Syntax error near "module"

    You shouldn't be assigning anything to a reg in it's declaration, this may or may not work in an FPGA some tools will use that as the power up state of the register.

    If you need to set a register...
  25. Replies
    13
    Views
    1,486

    Closed: Re: Error :Syntax error near "module"

    You should read a verilog book are at least an online tutorial


    reg [127:0] data_to_write = {32'h00AAAAAA, 32'hAAAAAAAA, 32'hAAAAAAAA, 31'hAAAAAAF, sw};

    to concatenate stuff in Verilog just...
Results 1 to 25 of 500
Page 1 of 20 1 2 3 4