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  1. Closed: Re: How to set_multicycle_path for latch in sta

    can you post the timing report and the exact command you have used?
  2. Closed: Re: How to set_multicycle_path for latch in sta

    I believe it means you missed something, maybe your from/to pair is not right. Also be aware that you can use wildcards if needed to capture multiple paths, say from signalA to arrayB
  3. Closed: Re: How to set_multicycle_path for latch in sta

    as long as there is a path between these two pins, it should work. after you issue the command, do a timing report from the same pin pair and check it.
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    Closed: Re: DRC rules for Double Pattern Test

    The most important rule is MxC1 to MxC2 distance (versus MxC1 to MxC1)
    Forbidden pitch rules are also very tricky
    odd cycle violations

    check this link:...
  5. Closed: Re: Floorplanning Guidelines for TSMC 7nm

    I am not a process engineer, so my explanation is really superficial. It has to do with how light is used to print the patterns and how it refracts and causes poorly printed shapes. If you keep it...
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    Closed: Re: Verilog and VHDL noise modelling

    if you don't have access to matlab, get octave.

    I still don't understand what you actually have as a system and why you insist on using a low level simulator. do you actually have a circuit with a...
  7. Closed: Re: Floorplanning Guidelines for TSMC 7nm

    gridded = in a grid, a pre-defined set of valid xy coordinates.
  8. Closed: Re: Floorplanning Guidelines for TSMC 7nm

    poly is unidirectional for many years now, it is the only way to keep pushing the process technology further. not only it is unidirectional, it is also gridded. there is a very specific way to lay...
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    Closed: Re: magic vlsi display units

    this seems unnecessary. lambda rules are sooooo outdated.
  10. Closed: Re: What are the typical lab characterization equipment used for testing Analog ICs?

    I have put together labs in different universities, and the typical culprits are: power sources, singal and function generators, oscilloscopes both digital and analog (both come in handy for...
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    Closed: Re: Verilog and VHDL noise modelling

    in theory, verilog/vhdl can be used just like a programming language and you can model anything you want.

    i think the real questions is whether these languages are good for this purpose. I would...
  12. [SOLVED]Closed: Re: P&R Buffer Reduction in a Shift Register

    cool, problem solved. just be careful when changing the max tran settings, there are usually guidelines for this coming from the std cell provider. I remember some really nice tables from ARM IP that...
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    Closed: Re: CADENCE is disabling functions alone

    You need to watch some really basic tutorials on how to use the tool.
  14. [SOLVED]Closed: Re: P&R Buffer Reduction in a Shift Register

    ok, let's ignore the timing report and assume it is normal.

    now let's try to figure out why the clk buffer is preferred over the normal buffer.
    first, they might have the same footprint and the...
  15. Closed: Re: How to do post layout simulation during digital ASIC design?

    my point is that I have never heard anyone referring to it as post layout simulation. we say annotated gate level simulation.

    and the closest I have seen people doing is hspice of critical paths,...
  16. [SOLVED]Closed: Re: P&R Buffer Reduction in a Shift Register

    just because they are clock tree buffers, doesn't mean they can't be used in the middle of the logic. this happens unless you prevent it with dont use statements

    I still can't understand your...
  17. [SOLVED]Closed: Re: P&R Buffer Reduction in a Shift Register

    this report looks very odd to me. are you using the clock signal as data and computing on it? (i can't see the attachment, so I don't know what the circuit is)
  18. Closed: Re: How to do post layout simulation during digital ASIC design?

    digital is not analog. there is no such thing as post layout simulation. design sizes are huge, simulators choke on them.

    you have to think about what you are trying to achieve here. meet timing?...
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    Closed: Re: Other end arrival time

    you need to propagate the clock. that is all.
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    Closed: Re: Other end arrival time

    this.

    also familiarize yourself with the timing debug tool, it is very helpful to visualize all these delay categories and where the numbers come from.
  21. Closed: Re: Design Compiler Input to Output Delay Constraints for A Shift Register

    This is normal. STA reports in->flop, flop->flop, flop->output. you don't have in->out paths.

    what am I missing?
  22. Closed: Re: How to convert DEF to LEF in Synopsys ICC2? (IC Compiler)

    I don't understand the reasoning here... I think you are going the wrong way about this. are you sure you understand how a LEF and a DEF are used in a design flow? what exactly are you trying to...
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    Closed: Re: Other end arrival time

    more details needed. is this a flop to flop path? is the clock already implemented during CTS? is clock propagated?
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    [SOLVED]Closed: Re: Zero Values For Internal Power

    more details needed. where are you seeing this? in the lib file? during synthesis? what cell is it coming from? all cells?
  25. Closed: Re: Verilog/SV: can assign + ternary produce latches?

    you have to realise they are very different. in the assign case, a is explicitly assigned to itself. this is not the case in the procedural assignments... and that is why students tend to overlook it.
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