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  1. Replies
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    Closed: Re: nport primitive and VerilogA

    If you mean the difference between input/output and inout ports , I think i do. But for the specific model, the ports are unidirectional.
    I am thinking in terms of block diagrams :
    The first block...
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    Closed: Re: nport primitive and VerilogA

    I understand that it is a linear black box, but how can I cascade correctly another black box that introduces non-linearities? Or it is just not possible?
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    Closed: Re: nport primitive and VerilogA

    I am just starting to model with VerilogA, so I would need a bit of more specific advice.
    The file generated from SP analysis can indeed be written as Z,Y,S parameters but how will this help?
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    Closed: Re: nport primitive and VerilogA

    Can you be a bit more specific about the calculation of a1,a2,b1,b2 and how will that help me?

    I would also prefer not to use S params but there is no other way as far as I know to properly model...
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    Closed: Re: nport primitive and VerilogA

    So I have to specify output impedance and the output voltage be expressed as the output current flowing through that output impedance?
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    Closed: Re: nport primitive and VerilogA

    You are right, if I map the ports to the pins of the module I get the correct S params.
    The thing is that I need to map the ports firstly in some internal nodes ,which will be the inputs of a...
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    Closed: nport primitive and VerilogA

    Hello all,
    I am instantiating an nport inside a VerilogA module and I map the pins of the module to the corresponding ports.
    The nport is reading an .s2p file that has been produced from the SP...
  8. Closed: Re: $freq while using AC analysis to access lookup table

    Hello pancho thank you for the reply,
    I havent had the time to test that piece of code but I am not sure if it will help me anyway. The nport way works really well until now!
  9. Closed: Re: $freq while using AC analysis to access lookup table

    Indeed the corresponding CDF parameters were not the same as the pins of the nport.
    For anyone's interest : pins p1,p2,p3... etc must be instantiated as port names t1,t2,t3... and pins m1,m2,m3.......
  10. Closed: Re: $freq while using AC analysis to access lookup table

    Hello and thank you for the reply.
    Instantiating the nport in VerilogA seems like a very good way to get the response I want. However, I can only connect the ports by order and not by name....
  11. Closed: Re: $freq while using AC analysis to access lookup table

    Thank you pancho, nport is indeed a way to associate frequency with magnitude. But it cannot be "translated" in VerilogA.
    Is there a way to only use VerilogA in order to manipulate the sweeped...
  12. Closed: Re: $freq while using AC analysis to access lookup table

    Thank you both for the replies.



    I use Spectre if that is what you mean.

    - - - Updated - - -


    Yes I am using verilogA to model a filter.
  13. Closed: $freq while using AC analysis to access lookup table

    Hello all,
    I have saved in a table the response of a filter. The table contains 2 columns; the first contains the frequency and the second the corresponding magnitude.
    I am building a model that...
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    Closed: PVS LVS error details

    Hello everyone,
    I am using Cadence PVS for the first time for LVS and DRC. In DRC the error fixing is straightforward as I can zoom in to the errors and fix them.
    In the LVS though, i can't find...
  15. Closed: Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

    Wow thanks for the answer dick_freebird, it will take some time to process this!
    @dr_kca , i will let you know when i get an answer. As far as the test is concerned, the signal pin is connected lets...
  16. Closed: Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

    I will contact them, thank you.
    BTW what do you mean by " should not attack the gate of a MOS "? If the input pad is connected to the gate of a MOS, the overvoltage should be seen at that terminal...
  17. Closed: Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

    Thank you for your answers, maybe i should contact.
    One last thing, i have noticed that if i connect a single test device ( e.g NMOS ) in the testbench then i get a proper discharge in all cases....
  18. Closed: Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

    Well due to CDB to OA conversion that i had to do, the schematic is messed up and i cant figure out the architecture of the cell. If there was a GGNMOS, it could explain the strange response. As far...
  19. Closed: Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

    You understood exactly what im trying to do. I do have power and ground cells as well, a power clamp between the power/ground rails and the I/O block on which im measuring the voltage after the "ESD...
  20. Closed: Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

    I mean that the PAD does not connect anywhere . The wire that should connect the PAD cell with the internal circuit is left floating and i measure the response of the testbench on that floating wire....
  21. Closed: Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

    Thank you for you answer . I do have a ground (otherwise the simulator wont work indeed ) but i dont have a circuit . The input pad ( that should connect to a terminal of a device lets say ) is left...
  22. Closed: Re: Problem in importing TSMC65 Standard Cells Library

    Are you sure about version 6.16? When i tried to give a path of a CDB library I wasnt able and had to convert it to OA
  23. Closed: Cadence virtuoso CDB to OA conversion ( schematic view problem )

    Hello,
    I am converting my library from CDB to OA format using the conversion toolbox. The conversion is completed without problem but the schematic appears completely messed up.
    And by messed up i...
  24. Closed: Re: Problem in importing TSMC65 Standard Cells Library

    I think they are in different format ( cdb ) than the one Virtuoso can understand ( oa ). So, use the Conversion Toolbox --> CDB to OA conversion, convert the library and then add the path of the OA...
  25. Closed: Re: Top level IO cells connection ( multiple IO voltages and global source use ) and

    Well i understand , thank you! If the cell now has, lets say, double diode embedded would I need to add an appropriate size GGNMOS for instance? Or another pair of double diodes?
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