Search:

Type: Posts; User: abdoboua

Search: Search took 0.02 seconds.

  1. Closed: Re: Simulation problem with MMSIM using smic 65nm technology

    I don't know which files to choose ,either .mdl or .ckt
  2. Closed: Simulation problem with MMSIM using smic 65nm technology

    Hello, I have a problem when simulating an inverter created with smic 65nm technology library.
    Here is a screenshot for the error messages

    154541

    Also I don't know what model files to choose,...
  3. Replies
    3
    Views
    348

    Closed: Re: Tech library problem

    the error says that cadence fails to load FreePDK45.tf
    it shows a lot of errors on the CIW
    154434
    154436
    154437
    154435
    should I change the hole tech library ?
    If yes, Is there another one that...
  4. Replies
    3
    Views
    348

    Closed: Tech library problem

    I have some problems with the NCSU_TechLib_FreePDK45:
    - I looked for the file divaDRC.rul for the DRC but I did not find it.
    - cadence is not able to integrate the FreePDK45.tf technology file.it...
  5. Replies
    1
    Views
    265

    Closed: Problem when installing Calibre

    when I type the comand ./install after copying the install.ixl folder to /opt/mentor , it gives me this error:

    *** Warning with: ./install
    The version of /usr/bin/java may not be correct!...
  6. Replies
    4
    Views
    284

    Closed: Re: pins of symbol and layout do not match

    conserning the PDK, the TechLib file contains just layouts ,and schematics are in the NCSU_Devices_FreePDK45 folder, this might be the problem, so I copied the schematics to each cell in the TechLib....
  7. Replies
    4
    Views
    284

    Closed: Re: pins of symbol and layout do not match

    it tells me that the symbol pins (G D S B) don't correspond to those of the layout(p D S)



    I don't know how to update pins to match them
  8. Replies
    4
    Views
    284

    Closed: pins of symbol and layout do not match

    I encountered this problem when I tried to generate layout from schematics automaticaly.

    154319

    154318

    after doing connctivity > update > binding I got this result
    Please help me to solve...
  9. Replies
    1
    Views
    268

    Closed: DRC problem with layout in cadence 617

    I don't have assura in toolbar.Des that mean that it is not enabled? that's why I tried to use Verify > DRC , when I have copied calibreDRC.rul to my tech folder(NCSU_TechLib_FreePDK45, I see an...
  10. Replies
    7
    Views
    460

    Closed: problem when zooming to see layers

    When I try to zoom in order to see the layers of the device ,I tried to increase stop in options > display but it shows me a " X " fill. I tried to change properties, but I don't know exactly the...
  11. Replies
    7
    Views
    460

    Closed: Re: Layout problem when trying to see layers

    I have a warning in WIC of cadence when adding a pmos_vtl to my layout, it says that :
    The Pcell super master: NCSU_TechLib_FreePDK45/pmos_vtl/layout is not a SKILL super master.
    The usage of...
  12. Replies
    7
    Views
    460

    Closed: Re: Layout problem when trying to see layers

    I tried to do what you have said, but I don't know exactly the properties to add, chould I modify cell properties or instance properties. Thank you for your help. 154277154278154279154280154281
  13. Replies
    7
    Views
    460

    Closed: Re: Layout problem when trying to see layers

    when I increase it, I get the "X" fill . I am using this 45nm technology : NCSU-FreePDK45-1.4.tar
  14. Replies
    7
    Views
    460

    Closed: Layout problem when trying to see layers

    When I try to zoom in order to see the layers of the device ,I tried to increase stop in options > display but it shows me a box with a cross on it.your help appreciated

    154227

    154228

    154229
  15. Replies
    1
    Views
    169

    Closed: Problem when starting cadence virtuoso

    when I try to start cadence virtuoso 6.17 with the command : virtuoso &
    an error message shows up:

    No protocol specified
    *WARNING* X Window Display Initialization failure
    *WARNING* (DISPLAY...
  16. Replies
    1
    Views
    197

    Closed: Cadence virtuoso problem

    I can't start cadence virtuoso with the command virtuoso & after installing the tools on a centos 6 VM(vmware).
    1- I created a folder in my home directory
    2- I copied cshrc file to it
    After...
  17. Replies
    1
    Views
    245

    Closed: Nand2 gate in magic vlsi

    I want to know why when I try to simulate the layout using irsim, the output gives me X.
Results 1 to 17 of 18