Type: Posts; User: filip.amator

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  1. Replies

    Closed: Re: channels in GNSS receiver

    Yes, according to the diagram this receiver can only process/track three channels.
  2. Replies

    Closed: Re: VGA to HDMI conversion

    You can get some HDMI examples from here:
  3. [SOLVED]Closed: Re: Request for clarification: multiplication and hardware multipliers blocks

    It depends on your tool -- read the manual.
  4. Replies

    Closed: Re: 1PPS Generator Module

    1. Go to SRS's website
    2. Products -> Time & Frequency Instruments
    3. Frequency Standards/Oscillators -> PRS10 10 MHz Rubidium Oscillator

    Ir is really easy.
  5. Replies

    Closed: Re: 1PPS Generator Module

    For example SRS FS725 Rubidium Frequency Standard
  6. Closed: Re: Is this old design a candidate for CPLD?

    You can do a simulation before you buy anything. Get Intel/Altera Quartus Prime (it's for free), you can build a logic circuit using block diagram a 74-family "virtual chips" and then compile it for...
  7. Closed: Re: Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    Ok, I see. Now this is oblivious for me why LEON3 soft-processor from grlib is using technology specific pads for every port from top level entity.
  8. Closed: Re: Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    But this functionality must be handled by SDRAM memory controller -- and after synthesis a proper bi-dir macro should be placed.
  9. [SOLVED]Closed: Re: RGMII problem with MAX 10 Development board

    Try using SignalTap logic analyzer to see if you can receive something.
    And the 88E1111 chip is hard to use because there is no public documentation for it. You have to pay and sign NDA to get any...
  10. Replies

    Closed: Re: FPGA vendors outside USA

    There is one European FPGA manufacturer of the rad-hard chips:
  11. Closed: Re: How to begin development on SOC (xilinx)

    You could also look at Cora Z7 board from Digilent - it's $99 and some pins are accessible over Pmod and Arduino like sheilds. The hardware itself is important but also docs provided by the pcb...
  12. Closed: Re: Using PLL(CD4046) to generate a 90° shifted signal, how to manage 10Hz - 1MHz?

    XOR phase detector will lock when there is 90deg of phase shift between signals.
  13. Closed: Re: Question about loop filter of CDR/PLL

    It seems that frequency detector here is used to bring two signals close to each other. When frequency difference is small then phase detector is enabled to make a phase lock.
  14. Closed: Re: Best way to interface with 14-bit 20MSample/s ADC

    You can always use Fast Ethernet to dump data into PC. UDP is quite easy to implement. It you don't plan to start a mass production of your device then take a simple eval board and attach your ADC...
  15. Replies

    Closed: Re: SD card multi block read

    Try with different SD card (newer, faster) and use the card in the parallel(4bit) mode.
  16. Replies

    Closed: Re: "RISC-V" CPU architecture

    Chinese firms sell electronics very cheap but they do not provide support and documentation on the sufficient level. It is good for doing a DIY but I would not use any hardware for serious commercial...
  17. Closed: Re: Tracking 'X' in the gate lavel simulation

    Ok, I found a source - a missing statement in a reset block.

    I see in my simulation (waveform preview in Modelsim) that the half of the rising edge is blue and half of it is green. The falling...
  18. Closed: Tracking 'X' in the gate lavel simulation

    I am trying to fix my design, it works in the ModelSim but doesn't work in the hardware. I ran gate level simulation (with the same test bench) but shortly after starting some debug at the output of...
  19. Replies

    Closed: Re: FPGA Module with 12 bit ADC

    Look at Cmod A7 with Artix - there is ADC 12bit 1 Msps inside the chip.
  20. Closed: Re: [MOVED] Why FPGAs are shipped with optional microcontrollers soft cores

    Have you tried to implement the handling of the FAT file system in the raw HDL? How do you think, how difficult it would be? And how expensive to contract a FPGA designer?
  21. Closed: Re: Microblaze and PmodCAN (Digilent IP core) in Vivado 2018.2

    This piece of code is designed for your CAN module. At one side it is connected to AXI bus and at another side must be connected to your hardware - your Pmod module.
  22. Closed: Re: Microblaze and PmodCAN (Digilent IP core) in Vivado 2018.2

    It is already connected on your design - there is a connection between AXI_LITE_GPIO of PmodCAN_0 and M03_AXI of microblaze_0_axi_perph.
  23. Replies

    Closed: Re: Simple Laser detector

    You can use cylindrical lens (or other optics or even diffraction pattern) to make a line-like laser dot from ordinary CW laser beam.
  24. Closed: Re: Why AXI DMAreads only 16 bit from DDR3 instead of 32 bits in my design?

    You can simulate whole design including Microblaze core and your compiled program using Vivado simulator. Start the simulation and see if the AXI master from Microblaze asks for whole 32 bits. Remove...
  25. Closed: Re: Demodulation of an laser interferometer signal

    Ordinary double balanced mixer has got linear range of +/- Pi/2, it means that the output from the mixer/phase detector will wrap if your vibrations are bigger that 1/4 of the wavelength of the...
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