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Type: Posts; User: KingDarius6288

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  1. Closed: Abbreviations of Layers in 65nm LSW

    Hi,
    how can I find what the abbreviations in LSW in tsmc65nm stand for? Is there any documentation to illustrate?
    Thanks
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    178

    Closed: DC level Change in Cadence

    Hi everyone,

    I have a question that might seem silly. I have an OTA that is going to be used in the attached configuration. The OTA ( an NMOS input single ended Folded Cascode, with a load...
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    546

    Closed: Varactor C-V Curves In Cadence

    Hi all,

    I want to obtain C-V curves of a varactor in cadence. I have some questions.

    1- In which simulation I can obtain C-V curves?

    2- For a single NMOS I tried DC sweep. I plotted Cgg-VDS...
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    246

    Closed: Re: OTA Closed Loop Test

    Thanks again FvM,

    This might seem silly, but I could not your idea. so let me put my question this way:
    1- If I design the OTA with fixed and equal DC levels for Vin+, Vin-, Vout, will it solve...
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    Closed: Re: OTA Closed Loop Test

    Thank you FvM. I have designed two OTAs with two different ranges. The first one has an input CM range of 0-0.2 and the second one has an input CM range of 0.4-0.7. Both of them have an output...
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    Closed: OTA Closed Loop Test

    Hi all;

    I have designed a two-stage OTA with Miller compensation. The first stage is Folded Cascode and the second one is a simple common source. The DC gain is 88dB and PM=35 deg. The load is a...
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    998

    Closed: Re: Opamp Design Procedure,

    Thank you frankrose,

    I know that the second question seems silly, but the problem is that in nm processes, the drain source voltage somehow becomes a headache. I was asking if someone knows a...
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    Closed: Opamp Design Procedure,

    Hi, I am new to opamp design field. Currently I want to design a two stage cascode opamp in 65 nm process, and I have two questions:

    1) Is there any reference that guides step by step design...
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