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Type: Posts; User: dick_freebird

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  1. Closed: Re: What is the difference between BVDSS and BVDS

    That would be something like BVdb_ but this is often not
    specified separately (especially if the foundry knows that
    lateral punchthrough or hot carrier reliability degradation
    happens well below...
  2. Closed: Re: Verilog-a code to latch analog voltages

    https://designers-guide.org/verilog-ams/index.html
  3. Closed: Re: Cadence Virtuoso - Border sheet locking / move to background

    You could also "take that A3 sheet private", and add a small
    instance/dwg rectangle as a "selection handle" (like maybe
    just around the title block) and then the sheet symbol will
    only be...
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    Closed: Re: Donors , Acceptors and Traps

    Impurities may or may not be trap sites.

    Dopant is desired to be substituted fully into the lattice
    and then it becomes electrically active (in a good way).
    Semiconductor properties are about...
  5. [SOLVED]Closed: Re: Do The Input And Output Capacitors Effect Efficiency In Switching Regulators

    Input filter capacitor ESR is a big deal in low voltage
    POL buck converters. The capacitor sees current
    equal to IOUT - charging during output switch "off"
    interval and discharging during "on"...
  6. Closed: Re: Help on Ocean scripting: run one analysis and use that results in another

    Can't help you with Ocean but used to do this a lot in
    cdsSpice, never could get the hang of it in bare Spectre
    or Ocean.

    But basically I'd make up a simple data structure (for
    example,...
  7. Closed: Re: Factors deciding Silicon Wafer Thickness

    Thinning (EOL) is needed more than before, for some of
    the low profile packaging that's become popular (not to
    mention 2.5D/3D integration). People are also doing
    extreme thinning to get...
  8. Closed: Re: Installing Cadence , Assura , EXT and MMSIM in Ubuntu

    I think you may only find a choice between various "seams"
    at which stuff falls apart.

    Ubuntu is great for people who don't want to mess with
    graphics setup. RHEL / CentOS didn't give me much...
  9. Closed: Re: Deaign of low ON resistor CMOS transmission gate

    If you care about things like charge injection then you may
    be forced to make D-G, S-G overlap capacitances equal and
    then you're also stuck with equal W and have to adjust the
    NMOS L for ohmic...
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    Closed: Re: Exact resistance output?

    If the resistance desired is "end to end" and the e-pot likewise
    (that is, not a shunt-to-ground or something like that) you could
    go for a higher bit count e-pot, or you could cascade two very...
  11. Closed: Re: Metal Oxide Semiconductor in strong Inversion

    Before we go any further, how about you quantify:


    "fast" and "slow" sweep time for a C-V measurement
    on normal equipment such as shown


    minority carrier lifetime in bulk regions
  12. Closed: Re: Metal Oxide Semiconductor in strong Inversion

    When you say "at the interface" it appears you assume that
    these are all carriers sitting in bulk silicon, leaning up against
    the wall just smoking a cigarette and pretty much free to do as
    they...
  13. Closed: Re: Metal Oxide Semiconductor in strong Inversion

    I believe you're looking at charge pumping C-V for the
    purpose of quantifying the trap density.

    The "frequency" high or low pertains to the trap lifetime
    (reciprocal). There are all kinds of...
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    Closed: Re: Switching power supply

    If you want all of those voltages from a single switch
    and single core you will see cross-regulation as an issue
    (one winner, N "also-rans").

    If you are in it for amusement / education, then...
  15. Closed: Re: How is the maximum inductor value in a technology process is determined

    One limit is the series resistance of the spiral, and
    somebody in the foundry design group might pick
    a number from an unspecified orifice and declare
    it a limit.

    If you need Q then you're...
  16. Closed: Re: Unable to plot the waveform while simulation in cadance specctre?

    You can declare a "marching waveform" which will update
    as you go.

    It's been a while but I don't recall needing the simulation
    to finish before plotting; getting partial plots is eomthing
    I...
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    Closed: Re: LDO Simulation Output Results

    Positive feedback when you wanted negative?

    Looks like you are only passing the dV/dt from supply
    to output and only when FETs are weak. Maybe you
    have something disconnected.

    You know what...
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    Closed: Re: Decoupling CAP using MOSFET?

    I have never encountered a technology where a
    capacitor-purpose dielectric is made thinner than the
    lowest voltage MOSFET gate. I'd be interested to see
    any examples otherwise.
  19. Closed: Re: Noise effects in a power source in ADS

    I'd tend to doubt that white noise is your biggest
    power supply "aggressor". A thing to characterize,
    sure, why not.

    But if you're after an estimate of in-application
    spectral purity, I...
  20. Closed: Re: How to measure differential signals using an Oscilloscope

    I like to use the "signal of interest" (or one side of the pair)
    for this because the CAL signal on most 'scopes is way lower
    frequency / edge rate than most of what I look at.

    You would of...
  21. Closed: Re: New fabrication of an old nmos processor from the 80s in a new semicond. technolo

    Back in the late '80s / early '90s I knew a guy out of TRW
    Redondo Beach who told me about InP digital chips they were
    doing, with 200GHz main clock.

    While detailed design databases are...
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    Closed: Re: LTSpice Noise Analyis

    I haven't really experienced anything I'd call "standard
    model design practices" in a pretty long IC design career.
    IME it's always a negotiation and you can't count on the
    noise params being...
  23. Closed: Re: Passing radiated EMC with an SMPS involves an element of luck...how much agree?

    Many of the "sprinkles" you mention look more like
    conducted emissions stuff. Of course power lead
    can do both.

    Why you'd expect a calculation to do anything for
    radiated emissions after the...
  24. Closed: Re: calibre LVS missing inductor (bad device detected)

    Look to your extract rules, the part that "should" recognize
    inductors. It probably wants some specific not-normal
    features tp do its job, because there's no real difference
    between an inductor...
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    Closed: Re: Decoupling CAP using MOSFET?

    "Issue", not really, provided that the supply "is what you
    think it is". Yes, there's gate ox defect density as a long
    term reliability detractor, but it's the same as what you've
    got going on...
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