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Type: Posts; User: wesleytaylor

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  1. Closed: Re: Real time voice encryption/decryption with FPGA

    Step1 Make sure you're not using any form of AES like CipherBlockChaining (at least not until you know where you are in the chain)
    Step2 Framing the data as outlined by #3 is a good place to start....
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    [SOLVED]Closed: Re: Modelsim clock signal

    Sweet. I found it useful for generating a ramp (counter), however interestingly it has no affect on the signal value.
    See picture
    154984

    wave create -pattern counter -startvalue 00000000...
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    [SOLVED]Closed: Re: Modelsim clock signal

    My version of modelsim/questasim doesn't even have create_wave.

    I have an option called force. In order to create a clock you force a toggle behaviour.

    I don't know where create_wave came from...
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    Closed: Re: How to compare variables name

    #2 I've noticed vpi handle in the vhdl standard? What is this?

    Is this the way the software processes the rtl code.

    Can you talk to modelsim/questasim or whatever software using these functions?
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    Closed: Re: Advanced VHDL book recommendation

    It's like groundhog day
    https://www.edaboard.com/showthread.php?375881-Is-the-quot-Gaisler-method-quot-of-writing-quot-structured-VHDL-quot-popular&p=1610157

    - - - Updated - - -

    What I would...
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    Closed: Re: Advanced VHDL book recommendation

    If you want to learn VHDL then read something written by Peter Ashenden or a book named as such online.

    If you want to write good structured code then read the following...
  7. Closed: Re: VHDL use of 'Z' std logic for bus, or should one use interconnect?

    Not ...bricked bricked, but dead to comms now. It works when I put the old build on, which used an interconnect setup with a huge slv of dtackbs AND reduced.

    I'm looking at the schematic and it's...
  8. Closed: VHDL use of 'Z' std logic for bus, or should one use interconnect?

    Hello all,

    Basically in simulation land the following works. However the question is can an FPGA handle tristating internally, because on hardware I've just bricked the device.

    OVERSEER takes...
  9. Closed: Re: vcom-1263 Error with generate and component instantiation

    Like many things in life, I'm force to do it through circumstance.

    The legacy code that I've inherited is like the stackoverflow question.

    They used for all statements in the wrong level of...
  10. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    I would like to confirm #8 worked for me.



    module x #(
    parameter sim_path = "string",
    ...
    )(
    ...
    )
  11. Closed: vcom-1263 Error with generate and component instantiation

    First see https://stackoverflow.com/questions/41860693/vhdl-warning-vcom-1263-configuration-specification-all-bcd-applies-to-no

    Now instead of including the

    for all : x use entity lib.x within...
  12. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    Looking at std 1364-2001 section 17. IS the function you're talking about sformat? I tried
    $display("%s", $sformat(my_str, "%s"));

    Needless to say this was a total failure. sim tool was expecting...
  13. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    #6 This is what I got with `define in quotes as per your comment

    Sim path = /home/P_1559_10030/iss_working/workspace/taylow00/simulation/sim_stimulus
    Result path =...
  14. [SOLVED]Closed: Re: Creating verilog define for filename based on input file path, string concatenati

    #2 As per the `else example, it works, however it's not flexible for other users.

    Situation is : User checkout repo from git. Within their workspace is a test_vectors directory. They develop tests...
  15. [SOLVED]Closed: Creating verilog define for filename based on input file path, string concatenation

    I want to be able to run a simulation with a test vector located in a repository. The repository will be determined by users credentials. The repository will not necessarily be a relative path to...
  16. [SOLVED]Closed: Verilog read-file task, unexpected behaviour

    Hello all,

    The following code is

    task TSK_READ_FILE;
    integer scan_file;
    reg [7:0] w_or_r;
    integer len;
    reg [31:0] addr;
    reg [31:0] data;
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    Closed: Re: VHDL code for 74hc4094

    See code....So basically
    1. You shift data into SO.
    2. Qstate is a snapshot of that.
    3. Qstate is deconstructed into Qx parts.

    Look for datasheet - see heading : 8-stage shift-and-store bus...
  18. Closed: Re: Vivado Taking A Long Time To Run Synthesis & Implementation

    You can get timestamps for when the various parts of par complete.

    This way you can get a feel for how long design init, opt_design, place_design and route design take.

    If you "pipelined" then...
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    [SOLVED]Closed: Re: Writing to an output file in VHDL

    variable padded_length : integer;
    Variable padding: std_logic_vector ((padding_length) downto 0) := (others => '0');

    Here is your problem
    Edit----------
    What probably happening is your computer...
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    Closed: Re: VHDL the maximum width of databus

    This question is flawed.

    VHDL will let you create a bus of any width.

    However certain FPGA's might limit the width because downstream there is a hard mac primitive that uses a certain...
  21. Closed: Re: Is there a way to implement generic map iostandard with ultrascale ibufds?

    I was not able to get attribute method working with a generate statement.

    I can get away with using a bespoke constraints .xdc file per design. However the plan was to use a purely hdl solution...
  22. [SOLVED]Closed: Re: Convert from STD_LOGIC to integer in VHDL

    std_logic but its nature is either 0 or 1.

    Do you mean std_logic_vector, furthermore when converting from interger back to std_logic_vector via unsigned you need to specify length
  23. Closed: Re: Is there a way to implement generic map iostandard with ultrascale ibufds?

    Having issues with the signal

    attribute iostandard of gpio_t(I) : signal is LVDS_25;

    Can't identify the signal.

    "attribute iostandard : string" seems happy being placed in block declarative...
  24. Closed: Is there a way to implement generic map iostandard with ultrascale ibufds?

    Hello all,

    I posted a similar question on xilinx forum, however I know this forum and community is much more informative and responsive.
    The goal it to create a configurable gpio pad ring for an...
  25. Closed: Mismatched pcie lanes ip core vs hardware.

    Hello all,

    I understand (ish) how pcie lanes work. I'm aware (ish) of down-plugging/ up-plugging, but I'm not entirely sure how an end point axi-pcie ip core which has been programmed to work with...
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