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Type: Posts; User: vivekroy

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  1. Replies
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    Closed: Re: Power Amplifier Design

    I do loadpull for the main amplifier at two points:
    1. Just before the peaking amplifier turns on and begins to significantly do "load modulation".
    2. When both the amplifiers are saturated.
    For...
  2. Closed: Re: How to increase high frequency output power

    The curve that circuitking has shared shows a very wide region of operation. Obtaining matching across such a wide range is quiet difficult. Typically, it would require the matching circuits to be...
  3. Closed: Re: How to increase high frequency output power

    Can you maybe elaborate on what you mean by "high frequency output power"? If you are referring to higher power at high frequency, then inductive peaking will not help (and of course you won't get...
  4. Closed: Re: Using VCVS as delay elements result in period signal rising and falling time chan

    Have you tried changing the maxstep parameter in your transient simulation?
  5. Closed: Re: Stability of a circuit and its role in design steps

    I know its not relevant to this thread particularly, but it is particularly relevant to HB not converging for conditionally stable circuits.

    I was once designing a PA using bipolar devices at...
  6. Closed: Re: Stability of a circuit and its role in design steps

    You only place the gate resistor to make it stable (Kf=1) which means your MAG and MSG are equal. You cannot get a gain more than MSG anyway. This is just to aid in the first iteration of doing a...
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    Closed: Re: RF Power Amplifier Design

    If you go from class A to class C, the gain peaking increases. Also your AM-PM distortion will have in a different way. But going to class C means your peak (and back-off) efficiency will increase. ...
  8. Closed: Re: What does "great linearity" means for a ring oscillator?

    Is this the paper you are talking about?
    https://ieeexplore.ieee.org/document/6123581
    The abstract itself defines what is meant by linearity.
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    Closed: Re: LNA circuit not working

    Are you sure you need a length of 150u and a width of 0.18u?
  10. Replies
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    Closed: Re: LNA circuit not working

    I just saw the mistake in your figure.. You have a w=0.18u and l=6u!!!! Good luck getting a gain out of that!!!

    Anyway, I am on vacations and I was getting bored..

    So I took your circuit, got...
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    Closed: Re: LNA circuit not working

    These are the issues I can see with your circuit..
    1. That Lbias value of 1nH is quiet low. And anyway your sinevoltage source has a DC value of 1.8V. Do you still need that biasing circuit in...
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    Closed: Re: EKV to BSIM Model Conversion

    https://ekv.epfl.ch/wp-content/uploads/2019/02/7_EKV_UMW04_Danica_Stefanovic.pdf

    https://www.edaboard.com/showthread.php?34852-BSIM3-4-to-EKV-model-translator

    TLDR; Reach out to the EPFL and...
  13. Closed: Re: How to generated different bit patterns in Cadence Virtuoso

    Check out step 5 from this link:

    Step 5: Go to Setup (from ADE-L)-> Simulation Files ... , under tab Vector Files , add the file you just created. For this example, it is ~/Cadence/vec/nand.vec
  14. Closed: Re: Effect of number of fingers and width of a transistor on Efficiency and power gai

    There have been quiet a few publications on this, and I request you to look up the work done by Patrick Reynaert on this.

    Efficiency depends on a lot of things and its hard to directly link to...
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    Closed: Re: input current of the integrator

    It does not change only if your gain is infinite. If your gain is finite, it does change.



    Doesn't it look like a capacitance of value A*C? (Miller effect!) And the impedance of a capacitor at...
  16. Closed: Re: Design pi/2 artificial transmission line using lumped elements

    If you want to see how increasing number of LC segments make a closer approximation to transmission line, check out this rather basic paper:...
  17. Closed: Re: How to measure the input reactance and output reactance of a MOSFET/gain stage

    Yes.. I see your point. I understand my mistake. Y11 = jw(Cgs+Cgd) (because the output would be shorted and both capacitances would come in parallel). Z11 expression will be longer but it will...
  18. Closed: Re: Why the inductor equation is different in this paper

    The delay matching by using lumped components using the approach shown in the figure completely disregards the effect of Cbc. Also, Cbe varies quiet a bit with the instantaneous voltage on the base....
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    Closed: Re: Doherty Power Amplifier

    Both these currents depend upon your load impedance. I normally designed Doherty by first designing the main amplifier, and then the peaking amplifier for optimum performance. Then I used to try and...
  20. Closed: Re: How to measure the input reactance and output reactance of a MOSFET/gain stage

    The expression for Cin is incorrect.
    Xc = abs(1/imag(1/zm(1 ?result "sp")) )
    Cin = 1 / (Xc*(2*3.14159*xval(zm(1 ?result "sp"))))

    Xc = 1/jwC ==> C = 1/(j*w*Xc)

    This Cin is Cgs + Av*Cgd

    ...
  21. Closed: Re: Design pi/2 artificial transmission line using lumped elements

    What he means is that you can only approximate a particular length of transmission line at a particular frequency by lumped components. Placing a length of transmission line only rotates your...
  22. Closed: Re: How to measure the input reactance and output reactance of a MOSFET/gain stage

    No.. If you are interested in the input impedance, look at ZM1 and for output impedance, look at ZM2. Not Z parameters. V1 = Z11*I1 + Z12*I2. If you only look at Z11, then you don't see the effect of...
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    Closed: Re: input current of the integrator

    Why not? Current aka charges are flowing to one of the plates of the capacitor, and the op-amp drains charges (of the same polarity) from the other plate, resulting in a rising potential difference...
  24. Closed: Re: Is it possible to have same optimum load through out the frequency range

    Loadpull is one of the ways to find an optimum impedance. But because this problem is rather non-linear, why not throw an optimizer at it and see if it can figure out a matching network that can give...
  25. Closed: Re: How to generated different bit patterns in Cadence Virtuoso

    Can't you just skip the output column in the vector file?
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