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Type: Forum Threads; User: rafimiet

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    • Replies: 5
    • Views: 545
    Last Post: 18th January 2018 14:19
    by std_match  Go to last post
    • Replies: 3
    • Views: 529
    Last Post: 3rd January 2018 15:19
    by ads-ee  Go to last post
  1. [SOLVED] Power Vs Area utilization in an FPGA

    Started by rafimiet, 28th December 2017 06:26
    • Replies: 8
    • Views: 657
    Last Post: 30th December 2017 15:23
    by TrickyDicky  Go to last post
  2. BRAM vs LUTRAM resources

    Started by rafimiet, 27th November 2017 07:16
    • Replies: 1
    • Views: 670
    Last Post: 27th November 2017 07:45
    by vGoodtimes  Go to last post
  3. [SOLVED] [Netlist 29-101] Netlist 'b0_decision' is not ideal for floorplanning

    Started by rafimiet, 25th November 2017 06:04
    • Replies: 4
    • Views: 851
    Last Post: 25th November 2017 20:48
    by vGoodtimes  Go to last post
  4. [SOLVED] concurrent vhdl code generating latches

    Started by rafimiet, 19th November 2017 10:10
    • Replies: 4
    • Views: 961
    Last Post: 19th November 2017 11:43
    by TrickyDicky  Go to last post
  5. [SOLVED] inout port in an inner component

    Started by rafimiet, 4th November 2017 06:07
    • Replies: 9
    • Views: 990
    Last Post: 5th November 2017 00:32
    by vGoodtimes  Go to last post
  6. [SOLVED] Using BRAM by infering and by using IP

    Started by rafimiet, 23rd October 2017 08:05
    • Replies: 10
    • Views: 607
    Last Post: 23rd October 2017 22:19
    by vGoodtimes  Go to last post
  7. [SOLVED] Two True-Dual-port rams in Zedboard

    Started by rafimiet, 21st October 2017 07:34
    • Replies: 3
    • Views: 443
    Last Post: 21st October 2017 10:48
    by TrickyDicky  Go to last post
  8. [SOLVED] Altering some bits of a RAM location

    Started by rafimiet, 6th October 2017 06:53
    • Replies: 2
    • Views: 418
    Last Post: 6th October 2017 08:10
    by TrickyDicky  Go to last post
  9. [SOLVED] clearing the contents of single port RAM

    Started by rafimiet, 4th October 2017 13:17
    • Replies: 13
    • Views: 883
    Last Post: 6th October 2017 04:28
    by vGoodtimes  Go to last post
  10. [Synth 8-27] complex assignment not supported

    Started by rafimiet, 5th October 2017 10:41
    • Replies: 4
    • Views: 652
    Last Post: 6th October 2017 04:23
    by vGoodtimes  Go to last post
  11. Morton Scan or Z-Scan in vhdl

    Started by rafimiet, 28th September 2017 05:51
    • Replies: 3
    • Views: 507
    Last Post: 29th September 2017 08:09
    by TrickyDicky  Go to last post
  12. Timing simulations in vivado

    Started by rafimiet, 14th September 2017 13:58
    • Replies: 4
    • Views: 459
    Last Post: 14th September 2017 17:56
    by TrickyDicky  Go to last post
  13. [SOLVED] "ERROR: [Common 17-165] Too many positional options when parsing

    Started by rafimiet, 13th September 2017 07:55
    • Replies: 7
    • Views: 1,096
    Last Post: 14th September 2017 10:51
    by TrickyDicky  Go to last post
  14. Initializing a very long vector with some repetition

    Started by rafimiet, 12th September 2017 12:59
    • Replies: 8
    • Views: 672
    Last Post: 13th September 2017 09:28
    by TrickyDicky  Go to last post
    • Replies: 7
    • Views: 518
    Last Post: 12th September 2017 10:44
    by TrickyDicky  Go to last post
  15. [SOLVED] ERROR:HDLParsers:3375

    Started by rafimiet, 11th September 2017 18:04
    • Replies: 1
    • Views: 326
    Last Post: 11th September 2017 18:57
    by TrickyDicky  Go to last post
  16. simulation in vivado vs ISIM(in Xilinx ISE)

    Started by rafimiet, 10th September 2017 05:30
    • Replies: 3
    • Views: 523
    Last Post: 11th September 2017 13:12
    by dpaul  Go to last post
  17. [SOLVED] how to locate the addresses of 1's in std_logic_vector

    Started by rafimiet, 9th September 2017 05:19
    • Replies: 12
    • Views: 716
    Last Post: 10th September 2017 19:33
    by vGoodtimes  Go to last post
  18. [SOLVED] Difference between combinational path delay and minimum period

    Started by rafimiet, 10th September 2017 06:56
    • Replies: 3
    • Views: 470
    Last Post: 10th September 2017 14:31
    by TrickyDicky  Go to last post
  19. [SOLVED]Closed: Parameters like speed, area and power after dumping on FPGA board

    Started by rafimiet, 22nd June 2017 07:54
    • Replies: 6
    • Views: 862
    Last Post: 22nd June 2017 11:28
    by vGoodtimes  Go to last post
    • Replies: 3
    • Views: 600
    Last Post: 25th January 2017 07:03
    by rafimiet  Go to last post
  20. [SOLVED]Closed: interfacing Artix 7 for image processing algorithm

    Started by rafimiet, 14th December 2016 11:12
    • Replies: 3
    • Views: 602
    Last Post: 16th December 2016 11:39
    by dpaul  Go to last post
  21. [SOLVED]Closed: variable size vector or array in VHDL

    Started by rafimiet, 13th December 2016 07:44
    • Replies: 2
    • Views: 799
    Last Post: 14th December 2016 06:28
    by vGoodtimes  Go to last post
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