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  1. [SOLVED]Closed: Re: [Synth 8-3332] Sequential element (ref_end_reg) is unused and will be removed fro

    I have a code section, where I don't understand if I can do away with variables. The functionality is as follows:


    The code that I wrote for this functionality involves a variable. The code is as...
  2. [SOLVED]Closed: Re: [Synth 8-3332] Sequential element (ref_end_reg) is unused and will be removed fro

    I got the point, but when I simulated the design, it was taking values greater than that...But you are right, may not be synthesizable...

    Can you elaborate a bit on this? I want to understand this...
  3. [SOLVED]Closed: [Synth 8-3332] Sequential element (ref_end_reg) is unused and will be removed from mo

    I have the following code

    ----------------------------------------------------------------------------------
    -- Company:
    -- Engineer:
    --
    -- Create Date: 10/31/2017 11:13:41 AM
    -- Design...
  4. [SOLVED]Closed: Re: Navigate LUT resources utilized by different components in a hiearchy in ISE 14.2

    No, I want something like this
    143675
  5. [SOLVED]Closed: Navigate LUT resources utilized by different components in a hiearchy in ISE 14.2

    In vivado, we can easily compile a hierarchy and navigate the resources utilized by each component. Is there some similar way to do so in ISE 14.2?
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    [SOLVED]Closed: Re: Power Vs Area utilization in an FPGA

    I agree with you...but
    From research point of view, if an architecture is already reported to be inefficient, as it consumes more area or provides low throughput (for example). You suggest a fix,...
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    [SOLVED]Closed: Re: Power Vs Area utilization in an FPGA

    But in case two boards have same technology(for example virtex 6, and zedboard use 6-input LUTs). Can we compare at least these two for resources? (Not speed or power).
    In general is there any...
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    [SOLVED]Closed: Comparison of area utilization among various FPGAs

    I have to compare my work to previous works done by other people. I am using Zedboard, they have used other boards. Some of the boards they have used are Virtex 6, Virtex 5, Virtex 2000E and Virtex...
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    [SOLVED]Closed: Re: Power Vs Area utilization in an FPGA

    Can you suggest me the best pdf for power consumption, that I can go through?
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    [SOLVED]Closed: Power Vs Area utilization in an FPGA

    I am working on area optimization of Image coders in FPGAs. I have modified an existing design, consuming more area into one that utilizes less area (functionality remains same). I want to ask if...
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    Closed: BRAM vs LUTRAM resources

    I am implementing a small memory, which after implementation takes the smallest possible BRAM block of 18kb in Zedboard. Then I force it not to take BRAM, so it takes the distributed RAM resources....
  12. [SOLVED]Closed: Re: [Netlist 29-101] Netlist 'b0_decision' is not ideal for floorplanning

    I have edited the code like this:

    architecture Behavioral of b0_decision is
    signal b0 : STD_LOGIC_VECTOR (N*N/4-1 downto 0) := (1 TO 3 => '1', OTHERS => '0');
    begin
    process(clk)
    begin
    if...
  13. [SOLVED]Closed: [Netlist 29-101] Netlist 'b0_decision' is not ideal for floorplanning

    I have a VHDL code as below

    entity b0_decision is
    GENERIC (N : integer := 256);
    Port ( b0_addr : in integer range 0 TO N*N/4-1;
    clk,update : in STD_LOGIC;
    valid :...
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    [SOLVED]Closed: Re: concurrent vhdl code generating latches

    If we use a process to replace Line 36 like this

    process(clk)
    begin
    if clk'event anf clk = '1' then
    thrsh1 <= thrsh;
    end if;
    end process;

    Would it then fix the error?If not, please make me...
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    [SOLVED]Closed: concurrent vhdl code generating latches

    I have to find maximum of a sequence. For that I have written a code below:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.NUMERIC_STD.ALL;

    entity threshold_calculator is
    GENERIC...
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    [SOLVED]Closed: Re: inout port in an inner component

    One sure thing it does is that it modifies the contents in b0 and I want b0 to reflect the changes. Please ignore the functionality of any component, as it is a part of a large design and to make it...
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    [SOLVED]Closed: Re: inout port in an inner component

    entity arch_D IS
    GENERIC (N : INTEGER := 16);
    Port ( clk,en_ref : in STD_LOGIC;
    valid,ref_end : out STD_LOGIC;
    byte_out : out STD_LOGIC_VECTOR (7 downto 0));
    end arch_D;...
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    [SOLVED]Closed: Re: inout port in an inner component

    Then outside the port mapping of component, I have to assign X_out into X_in?
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    [SOLVED]Closed: inout port in an inner component

    I have read many questions regarding inout port in vhdl. Given the details, I am a bit hesitated to use a tristate buffer for that. Now my question is like this:
    I have three components A,B,C in a...
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    [SOLVED]Closed: Re: Using BRAM by infering and by using IP

    Would one address get me 11 bits from 11 locations of the RAM then(in one clock cycle)?Is that possible?
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    [SOLVED]Closed: Re: Using BRAM by infering and by using IP

    The resources used Post-Implementation at depth = 65536, width = 11 are as follows:
    BRAM = 22
    IO = 79
    BUFG = 1
    The resources used Post-Implementation at depth = 65536, width = 18 are as follows:...
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    [SOLVED]Closed: Re: Using BRAM by infering and by using IP

    I understand the point here

    But when I use a BRAM of (depth = 256) width=11 bits and width=18 bits, the implementation results show different resource utilization. Practically, the resources...
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    [SOLVED]Closed: Using BRAM by infering and by using IP

    In zedboard, we have 140 block RAMs which can be used in following configurations(a few given here) as per the user guide:
    DEPTH WIDTH SIZE
    1024 18 18kb
    2048 ...
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    [SOLVED]Closed: Re: Two True-Dual-port rams in Zedboard

    It is a large code, I don't understand how can I post the code.
    Secondly, Yes it is when I simulate the code.
    The question I ask is:
    Is it possible to use two true dual-port RAMs, and read from...
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    [SOLVED]Closed: Two True-Dual-port rams in Zedboard

    I have to use two small true dual port RAMs in zedboard(say MEMa and MEMb).
    First part of code does this:
    1. Get data at I/O port
    2. Write on both ports of RAMa
    Second part of code does this:...
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