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Type: Posts; User: pancho_hideboo

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1. ## Thread: Identical gain stages in Distributed amplifier:are they paralllel or cascaded?

by pancho_hideboo
Replies
1
Views
87

### Closed: Re: Identical gain stages in Distributed amplifier:are they paralllel or cascaded?

No one can understand what you want to mean.
Describe correctly.
2. ## Thread: Frequency as a variable in an instance

by pancho_hideboo
Replies
1
Views
89

### Closed: Re: Frequency as a variable in an instance

It depends on what simulator you use.
3. ## Thread: Interpretation of AoD(Angle of Departure)

by pancho_hideboo
Replies
1
Views
454

### Closed: Re: Interpretation of AoD(Angle of Departure)

I can interpret AoD by Equivalent Spatial Sampling by Virtual RX Array.
So AoD is same as AoA.
4. ## Thread: How to get phase of par equations in HSPICE

by pancho_hideboo
Replies
1
Views
166

### Closed: Re: How to get phase of par equations in HSPICE

par('atan( (ii(R1)+ii(R2))/(ir(R1)+ir(R2)) )')

by pancho_hideboo
Replies
3
Views
136

6. ## Thread: deviding Y value by X values in Cadence Virtuoso calculator

by pancho_hideboo
Replies
9
Views
302

### Closed: Re: deviding Y value by X values in Cadence Virtuoso calculator

See attached figure.

Rather I suspect your test bench, since you still can not understand linear circut basics such as differentail mode, common mode, ideal transfomer and etc. at all....
7. ## Thread: deviding Y value by X values in Cadence Virtuoso calculator

by pancho_hideboo
Replies
9
Views
302

### Closed: Re: deviding Y value by X values in Cadence Virtuoso calculator

Surely see legend of ViVA.
imag() is not applied.

Simply apply imag() in numerator.

If you plot complex value without applying any function, Cadence ViVA plots absolute value.
8. ## Thread: In distributed amplifiers, is it total input capacitance of the gain stage or Cgs

by pancho_hideboo
Replies
4
Views
298

### Closed: Re: In distributed amplifiers, is it total input capacitance of the gain stage or Cgs

No.
It is a LC ladder or an approximation model of line.
9. ## Thread: Gate Level Simulation

by pancho_hideboo
Replies
11
Views
459

### Closed: Re: Gate Level Simulation

It is Gate-Level-HDL.

I don’t think he reaches to SDF annotation.

Simply his purpose requires standard cell library or technology library.
10. ## Thread: deviding Y value by X values in Cadence Virtuoso calculator

by pancho_hideboo
Replies
9
Views
302

### Closed: Re: deviding Y value by X values in Cadence Virtuoso calculator

No.
It is absolute value.

11. ## Thread: deviding Y value by X values in Cadence Virtuoso calculator

by pancho_hideboo
Replies
9
Views
302

### Closed: Re: deviding Y value by X values in Cadence Virtuoso calculator

You have to apply imag() for numerator.

Generally Capacitance is nearly constant over frequency.
12. ## Thread: deviding Y value by X values in Cadence Virtuoso calculator

by pancho_hideboo
Replies
9
Views
302

13. ## Thread: Operational amplifier driving capability test

by pancho_hideboo
Replies
11
Views
272

### Closed: Re: Operational amplifier driving capability test

Load current could be sink and source direction.
So simple DC current source is not appropriate as load.
14. ## Thread: Operational amplifier driving capability test

by pancho_hideboo
Replies
11
Views
272

### Closed: Re: Operational amplifier driving capability test

Simply do load value sweep with observing THD or SNDR.

15. ## Thread: Converting verilog code into a symbol during AMS simulation

by pancho_hideboo
Replies
5
Views
178

### Closed: Re: Converting verilog code into a symbol during AMS simulation

Simply edit manually.
16. ## Thread: Converting verilog code into a symbol during AMS simulation

by pancho_hideboo
Replies
5
Views
178

### Closed: Re: Converting verilog code into a symbol during AMS simulation

Simply they are bus pins.
17. ## Thread: Gate Level Simulation

by pancho_hideboo
Replies
11
Views
459

### Closed: Re: Gate Level Simulation

No one can understand what you mean.
Express in detail with correct terminology.

Do you mean Gate-Level-HDL which is synthesized from RTL-HDL ?
18. ## Thread: Differential and common mode input resistance of the fully diffferential amplifier

by pancho_hideboo
Replies
22
Views
920

### Closed: Re: Differential and common mode input resistance of the fully diffferential amplifie

Show me netlist regarding signal sources, loads, balun and analysis statements.

by pancho_hideboo
Replies
3
Views
203

Yes........
20. ## Thread: What happens to output power and 3 BW in this circuit

by pancho_hideboo
Replies
1
Views
127

### Closed: Re: What happens to output power and 3 BW in this circuit

Why do you set three ports.
Where is driving point ?

What do you expect ?

by pancho_hideboo
Replies
3
Views
203

### Closed: Re: Why should LNA also care about IIP3?

Assume three mobile phones, A, B and C.
Their Distances from base station are different.
Distance of A is small.
Distance of B and C is large.

Consider tx power control from base station.
TX...
22. ## Thread: Verilog-a code to latch analog voltages

by pancho_hideboo
Replies
7
Views
333

### Closed: Re: Verilog-a code to latch analog voltages

This is not transparent latch.

For V(Clk2)=High, V(out)=V(in) ; Tranparent
Then V(in) is captured at negative edge of V(Clk2).
V(out) is constant during V(Clk2)=Low ; Hold Mode.

by pancho_hideboo
Replies
15
Views
558

### Closed: Re: Problem in plotting I/O waveform in Cadence

by pancho_hideboo
Replies
15
Views
558

### Closed: Re: Problem in plotting I/O waveform in Cadence

Can you understand netlist ?
Show me netlist.

by pancho_hideboo
Replies
2
Views
229

### Closed: Re: DNL/INL Measurement in Cadence for DAC

This is a static DNL.

Evaluation of static DNL and INL does not require Histogram.

On the other hand, dynamic DNL requires Histogram.
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