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Type: Posts; User: pancho_hideboo

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  1. Closed: Re: Identical gain stages in Distributed amplifier:are they paralllel or cascaded?

    No one can understand what you want to mean.
    Describe correctly.
  2. Closed: Re: Frequency as a variable in an instance

    It depends on what simulator you use.
  3. Closed: Re: Interpretation of AoD(Angle of Departure)

    I can interpret AoD by Equivalent Spatial Sampling by Virtual RX Array.
    So AoD is same as AoA.
  4. Closed: Re: How to get phase of par equations in HSPICE

    par('atan( (ii(R1)+ii(R2))/(ir(R1)+ir(R2)) )')
  5. Closed: Re: Phase Difference calculation in cadence.

    Ask Cadence’s Design Service since you use Outsource Design Service in Cadence.
  6. Closed: Re: deviding Y value by X values in Cadence Virtuoso calculator

    See attached figure.

    Rather I suspect your test bench, since you still can not understand linear circut basics such as differentail mode, common mode, ideal transfomer and etc. at all....
  7. Closed: Re: deviding Y value by X values in Cadence Virtuoso calculator

    Surely see legend of ViVA.
    imag() is not applied.

    Simply apply imag() in numerator.

    If you plot complex value without applying any function, Cadence ViVA plots absolute value.
  8. Closed: Re: In distributed amplifiers, is it total input capacitance of the gain stage or Cgs

    No.
    It is a LC ladder or an approximation model of line.
  9. Replies
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    459

    Closed: Re: Gate Level Simulation

    It is Gate-Level-HDL.

    I don’t think he reaches to SDF annotation.

    Simply his purpose requires standard cell library or technology library.
  10. Closed: Re: deviding Y value by X values in Cadence Virtuoso calculator

    No.
    It is absolute value.

    Don’t believe Cadence ADE.
  11. Closed: Re: deviding Y value by X values in Cadence Virtuoso calculator

    Simply your equation is wrong.
    You have to apply imag() for numerator.

    Generally Capacitance is nearly constant over frequency.
  12. Closed: Re: deviding Y value by X values in Cadence Virtuoso calculator

    See https://www.edaboard.com/showthread.php?292767#4
  13. Closed: Re: Operational amplifier driving capability test

    Load current could be sink and source direction.
    So simple DC current source is not appropriate as load.
  14. Closed: Re: Operational amplifier driving capability test

    Simply do load value sweep with observing THD or SNDR.

    However load could be capacitive.
  15. Closed: Re: Converting verilog code into a symbol during AMS simulation

    Simply edit manually.
  16. Closed: Re: Converting verilog code into a symbol during AMS simulation

    Simply they are bus pins.
  17. Replies
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    459

    Closed: Re: Gate Level Simulation

    No one can understand what you mean.
    Express in detail with correct terminology.

    Do you mean Gate-Level-HDL which is synthesized from RTL-HDL ?
  18. Closed: Re: Differential and common mode input resistance of the fully diffferential amplifie

    Show me netlist regarding signal sources, loads, balun and analysis statements.
  19. Closed: Re: Why should LNA also care about IIP3?

    Yes........
  20. Closed: Re: What happens to output power and 3 BW in this circuit

    Why do you set three ports.
    Where is driving point ?

    What do you expect ?
  21. Closed: Re: Why should LNA also care about IIP3?

    Assume three mobile phones, A, B and C.
    Their Distances from base station are different.
    Distance of A is small.
    Distance of B and C is large.

    Consider tx power control from base station.
    TX...
  22. Closed: Re: Verilog-a code to latch analog voltages

    This is not transparent latch.

    For V(Clk2)=High, V(out)=V(in) ; Tranparent
    Then V(in) is captured at negative edge of V(Clk2).
    V(out) is constant during V(Clk2)=Low ; Hold Mode.
  23. Closed: Re: Problem in plotting I/O waveform in Cadence

    See https://www.edaboard.com/showthread.php?345554/page3#59
  24. Closed: Re: Problem in plotting I/O waveform in Cadence

    Can you understand netlist ?
    Show me netlist.
  25. Closed: Re: DNL/INL Measurement in Cadence for DAC

    This is a static DNL.

    Evaluation of static DNL and INL does not require Histogram.

    On the other hand, dynamic DNL requires Histogram.
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